From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keir Fraser Subject: Re: [PATCH] X86: cpuid faulting feature enable Date: Fri, 01 Jul 2011 19:02:51 +0100 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: "Liu, Jinsong" , Jan Beulich Cc: "Tian, Kevin" , "xen-devel@lists.xensource.com" , "Shan, Haitao" , "Li, Xin" List-Id: xen-devel@lists.xenproject.org On 01/07/2011 18:48, "Liu, Jinsong" wrote: >> Down to a particular stepping? That surely doesn't make sense for >> anything but your own experimenting. > > Yes, it's some ugly. > Currently cpuid faulting is not a architecturally commited feature, and, some > other Intel processors (which do not has cpuid faulting feature) also has > 0xceh MSR. > Hence I use current way for safe. However, I marked it as FIXME to update in > the future accordingly. But Intel's own supporting document states that bit 31 of the PLATFORM_INFO MSR should be sufficient to identify the cpuid faulting feature. Do you really need the stepping check as well? Could you just do a rdmsr_safe read-and-check of PLATFORM_INFO_MSR[31] instead? It would be okay for other Intel CPUs to have MSR 0xce, so long as they don't set bit 31... -- Keir