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[84.0.31.213]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c29de48755asm6606766b.24.2026.09.15.10.23.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 10:23:08 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: Alex Deucher Cc: amd-gfx@lists.freedesktop.org, Marek =?UTF-8?B?T2zFocOhaw==?= , Alex Deucher , Christian =?UTF-8?B?S8O2bmln?= , Tvrtko Ursulin , pierre-eric.pelloux-prayer@amd.com, Natalie Vock , Lijo Lazar , Felix Kuehling Subject: Re: [PATCH 00/12] RFC: drm/amdgpu/sdma: Refactor SDMA v4 and older functions to be per-instance Date: Tue, 15 Sep 2026 19:23:07 +0200 Message-ID: In-Reply-To: References: <20260907203316.159103-1-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Friday, September 11, 2026 9:00:07=E2=80=AFPM Central European Summer Ti= me Alex=20 Deucher wrote: > On Mon, Sep 7, 2026 at 4:40=E2=80=AFPM Timur Krist=C3=B3f =20 wrote: > > This series applies on top of my previous series: > > "Improve existing SDMA queue resets" (currently under review) > >=20 > > Prepare the code for implementing recovery for > > SDMA v4 and all older SDMA (and SI DMA) versions. > > Reorganize the SDMA 4.0 code so that the functions that are > > responsible for managing the SDMA engines take an instance ID > > as an argument. > >=20 > > This makes it possible to manage the SDMA instances > > independently of each other, which will enable us to > > also use these functions to implement resetting and > > recovering them independently. (The actual recovery > > implementation will be in a follow-up patch series > > which I will submit after this one is accepted.) >=20 > This series looks fine to me, although I think I would prefer to apply > it along with the relevant soft reset changes to avoid churning the > code until each family is ready. E.g., apply the cik_sdma refactor > along with the CIK soft reset support, etc. Unless you have something > else in mind. Thank you Alex. My plan is the following: 1. I would like to first refactor the functions for every SDMA IP block ver= sion=20 to be per-instance. 2. Then, I'd like to improve the soft reset code, more specifically the mul= ti- ring reset helpers and amdgpu_device_ip_soft_reset() to make them aware of = IP=20 block instances and change SDMA v4.4.2, v5.0 and v5.2 over to use that code. 3. With all of that out of the way, it will be pretty easy to hook up the s= ame=20 soft reset mechanism for SI, CIK, VI as well. 4. At that point, we should also consider if we want soft reset for SDMA v6= =20 and v7. Technically these versions support proper queue reset through the M= ES,=20 but in practice I've seen the MES fail so often that I wouldn't consider it= =20 stable. This RFC is basically a prototype for step (1) and only takes care of SDMA = v4=20 and older just to show how I imagine doing the refactor. If you like this=20 direction, I would like to do the same for all IP versions before moving=20 forward with soft reset changes and other refactors. I prefer to do this fi= rst=20 for all IP versions because I think it's important to have consistency with= in=20 the code base regarding how the SDMA is programmed. What do you think, would that be OK for you? I understand this causes code churn, sorry about that. Thanks & best regards, Timur >=20 > > Timur Krist=C3=B3f (12): > > drm/amdgpu/sdma: Refactor SI DMA functions to be per instance > > drm/amdgpu/sdma: Refactor SI DMA clock gating functions to be > > =20 > > per-instance > > =20 > > drm/amdgpu/sdma: Refactor CIK SDMA functions to be per instance > > drm/amdgpu/sdma: Refactor CIK SDMA clock gating functions to be > > =20 > > per-instance > > =20 > > drm/amdgpu/sdma: Refactor SDMA v2.4 functions to be per instance > > drm/amdgpu/sdma: Refactor SDMA v2.4 golden registers to be > > =20 > > per-instance > > =20 > > drm/amdgpu/sdma: Refactor SDMA v3.0 functions to be per instance > > drm/amdgpu/sdma: Refactor SDMA v3.0 clock gating functions to be > > =20 > > per-instance > > =20 > > drm/amdgpu/sdma: Refactor SDMA v3.0 golden registers to be > > =20 > > per-instance > > =20 > > drm/amdgpu/sdma: Refactor SDMA v4.0 functions to be per instance > > drm/amdgpu/sdma: Refactor SDMA v4.0 clock gating functions to be > > =20 > > per-instance > > =20 > > drm/amdgpu/sdma: Refactor SDMA v4.0 golden registers to be > > =20 > > per-instance > > =20 > > drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 322 +++++++------- > > drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 232 +++++----- > > drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 561 ++++++++++++++---------- > > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 577 +++++++++++++++---------- > > drivers/gpu/drm/amd/amdgpu/si_dma.c | 160 ++++--- > > 5 files changed, 1043 insertions(+), 809 deletions(-) > >=20 > > -- > > 2.55.0