From mboxrd@z Thu Jan  1 00:00:00 1970
From: Keir Fraser <keir@xen.org>
Subject: Re: [PATCH] x86/PCI: pass correct register value to XSM
Date: Fri, 22 Jun 2012 09:53:51 +0100
Message-ID: <CC09F12F.4374D%keir@xen.org>
References: <4FE44A0A020000780008B4AC@nat28.tlf.novell.com>
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To: Jan Beulich <JBeulich@suse.com>, Daniel De Graaf <dgdegra@tycho.nsa.gov>
Cc: xen-devel@lists.xen.org
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On 22/06/2012 09:33, "Jan Beulich" <JBeulich@suse.com> wrote:

> When attempting to use AMD's extension to access the extended PCI config
> space, only the low byte of the register number was being passed to XSM.
> Include the correct value of the register if this feature is enabled;
> otherwise, bits 24-30 of port cf8 are reserved, so disallow the invalid
> access.
> 
> Signed-off-by: Daniel De Graaf <dgdegra@tycho.nsa.gov>
> 
> Don't fail the permission check except when the MSR can't be read.
> 
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

Acked-by: Keir Fraser <keir@xen.org>

> --- a/xen/arch/x86/traps.c
> +++ b/xen/arch/x86/traps.c
> @@ -1701,6 +1701,18 @@ static int pci_cfg_ok(struct domain *d,
>              return 0;
>      }
>      start = d->arch.pci_cf8 & 0xFF;
> +    /* AMD extended configuration space access? */
> +    if ( (d->arch.pci_cf8 & 0x0F000000) &&
> +         boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
> +         boot_cpu_data.x86 >= 0x10 && boot_cpu_data.x86 <= 0x17 )
> +    {
> +        uint64_t msr_val;
> +
> +        if ( rdmsr_safe(MSR_AMD64_NB_CFG, msr_val) )
> +            return 0;
> +        if ( msr_val & (1ULL << AMD64_NB_CFG_CF8_EXT_ENABLE_BIT) )
> +            start |= (d->arch.pci_cf8 >> 16) & 0xF00;
> +    }
>      end = start + size - 1;
>      if (xsm_pci_config_permission(d, machine_bdf, start, end, write))
>          return 0;
> 
> 
>