From: wbarak@gmail.com (Barak Wasserstrom)
To: linux-arm-kernel@lists.infradead.org
Subject: GIC affinity and edge trigger
Date: Thu, 20 Sep 2012 19:22:28 +0300 [thread overview]
Message-ID: <CC811D74.ECFF%wbarak@gmail.com> (raw)
Hello,
I'm currently using linux kernel 2.6.38 with SMP enabled.
I have an interrupt which is a pulse and therefore I set the trigger to
positive edge.
Due to the fact that each CPU sees its own GIC distributor memory space,
only the CPU that executed request_irq has the trigger type set to positive
edge, while the others remain level.
Moreover, gic_set_cpu always defines the GIC distributor target to be CPU0.
So only CPU0 target is enabled + trigger is set to edge only for one CPU and
thus not always do I get the interrupt.
Can you please help me understand what I'm doing wrong, or misunderstand?
Regards,
Barak
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next reply other threads:[~2012-09-20 16:22 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-20 16:22 Barak Wasserstrom [this message]
2012-09-24 14:26 ` GIC affinity and edge trigger Marc Zyngier
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