From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keir Fraser Subject: Re: [PATCH] x86/emul: only emulate possibly operand sizes for POPA Date: Thu, 08 Nov 2012 09:08:34 +0000 Message-ID: References: <509B7C9C02000078000A725F@nat28.tlf.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <509B7C9C02000078000A725F@nat28.tlf.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: xen-devel List-Id: xen-devel@lists.xenproject.org On 08/11/2012 08:34, "Jan Beulich" wrote: >> I did wonder. The top halves of 64b registers are not used in compatibility >> mode. Are their contents at all guaranteed to be >> maintained/updated/preserved in any meaningful way across transitions into >> and out of compatibility mode? I wasn't aware they were, and in that case >> the cast and comment are indeed pointless. > > There's no architectural guarantee, but that's how CPUs work. > The important aspect (from an information leak perspective) is > that upper halves don't get zeroed explicitly when switching > between compatibility and 64-bit modes. > > Now we can of course utilize that read_ulong() already does the > zero extension (but if it didn't, we would leak stack contents here, > so it may still be worth a comment), to the net effect of The concern over information leak is fair. Just leave the code line as-is then with the explicit cast and end-of-line comment. K.