From mboxrd@z Thu Jan  1 00:00:00 1970
From: Keir Fraser <keir.xen@gmail.com>
Subject: Re: [PATCH] x86: use "R" constraint for
	fxsaveq/fxrstorq enforcement
Date: Tue, 13 Aug 2013 18:34:20 +0100
Message-ID: <CE302CAC.5AC15%keir.xen@gmail.com>
References: <520A705E02000078000EB96B@nat28.tlf.novell.com>
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To: Jan Beulich <JBeulich@suse.com>, xen-devel <xen-devel@lists.xenproject.org>
List-Id: xen-devel@lists.xenproject.org

On 13/08/2013 16:43, "Jan Beulich" <JBeulich@suse.com> wrote:

> I became aware of this constraint's (referring to all legacy registers
> in one go) existence by (accidentally) noticing Linux commit 82024135
> ("x86-64, fpu: Simplify constraints for fxsave/fxtstor").
> 
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

Assuming it is available on all our supported versions of gcc:

Acked-by: Keir Fraser <keir@xen.org>

> --- a/xen/arch/x86/i387.c
> +++ b/xen/arch/x86/i387.c
> @@ -96,8 +96,7 @@ static inline void fpu_fxrstor(struct vc
>              ".previous                \n"
>              _ASM_EXTABLE(1b, 2b)
>              :
> -            : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4),
> -              "cdaSDb" (fpu_ctxt) );
> +            : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4), "R" (fpu_ctxt) );
>          break;
>      case 4: case 2:
>          asm volatile (
> @@ -162,7 +161,7 @@ static inline void fpu_fxsave(struct vcp
>           * addressing mode that doesn't require extended registers.
>           */
>          asm volatile ( REX64_PREFIX "fxsave (%1)"
> -                       : "=m" (*fpu_ctxt) : "cdaSDb" (fpu_ctxt) );
> +                       : "=m" (*fpu_ctxt) : "R" (fpu_ctxt) );
>  
>          /*
>           * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
> 
> 
>