Re: [PATCH v4 1/6] target/ppc: Fix instruction loading endianness in alignment interrupt

["Nicholas Piggin" <npiggin@gmail.com>]

On Wed Jun 14, 2023 at 3:51 PM AEST, Anushree Mathur wrote:
>
> On 5/30/23 18:55, Nicholas Piggin wrote:
> > powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
> > after cpu_ldl_code(). This corrects DSISR bits in alignment
> > interrupts when running in little endian mode.
> >
> > Reviewed-by: Fabiano Rosas<farosas@suse.de>
> > Signed-off-by: Nicholas Piggin<npiggin@gmail.com>
> > ---
> >   target/ppc/excp_helper.c | 22 +++++++++++++++++++++-
> >   1 file changed, 21 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> > index c13f2afa04..0274617b4a 100644
> > --- a/target/ppc/excp_helper.c
> > +++ b/target/ppc/excp_helper.c
> > @@ -133,6 +133,26 @@ static void dump_hcall(CPUPPCState *env)
> >                     env->nip);
> >   }
> >   
> > +#ifdef CONFIG_TCG
> > +/* Return true iff byteswap is needed in a scalar memop */
> > +static inline bool need_byteswap(CPUArchState *env)
> > +{
> > +    /* SOFTMMU builds TARGET_BIG_ENDIAN. Need to swap when MSR[LE] is set */
> > +    return !!(env->msr & ((target_ulong)1 << MSR_LE));
> > +}
> > +
> > +static uint32_t ppc_ldl_code(CPUArchState *env, abi_ptr addr)
>
> This hunk fails to compile with configure --disable-tcg

I don't see how since it's inside CONFIG_TCG. Seems to work here.
You don't have an old version of the patch applied?

What configure options exactly?

Thanks,
Nick