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charset=UTF-8 Date: Tue, 20 Jun 2023 20:45:13 +1000 Message-Id: Cc: , "Daniel Henrique Barboza" , "Richard Henderson" , =?utf-8?q?Alex_Benn=C3=A9e?= , "Thomas Huth" , "Harsh Prateek Bora" , "Kautuk Consul" Subject: Re: [PATCH 0/4] target/ppc: TCG SMT support for spapr From: "Nicholas Piggin" To: =?utf-8?q?C=C3=A9dric_Le_Goater?= , X-Mailer: aerc 0.14.0 References: <20230605112323.179259-1-npiggin@gmail.com> <43ca9ac8-d383-42fd-ca29-f7cdd18d701d@kaod.org> <2756fa81-9ab8-0b15-a69e-726b47a43d41@kaod.org> In-Reply-To: <2756fa81-9ab8-0b15-a69e-726b47a43d41@kaod.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue Jun 20, 2023 at 8:27 PM AEST, C=C3=A9dric Le Goater wrote: > On 6/20/23 12:12, Nicholas Piggin wrote: > > On Wed Jun 7, 2023 at 12:09 AM AEST, C=C3=A9dric Le Goater wrote: > >> On 6/5/23 13:23, Nicholas Piggin wrote: > >>> Previous RFC here > >>> > >>> https://lists.gnu.org/archive/html/qemu-ppc/2023-05/msg00453.html > >>> > >>> This series drops patch 1 from the previous, which is more of > >>> a standalone bugfix. > >>> > >>> Also accounted for Cedric's comments, except a nicer way to > >>> set cpu_index vs PIR/TIR SPRs, which is not quite trivial. > >>> > >>> This limits support for SMT to POWER8 and newer. It is also > >>> incompatible with nested-HV so that is checked for too. > >>> > >>> Iterating CPUs to find siblings for now I kept because similar > >>> loops exist in a few places, and it is not conceptually > >>> difficult for SMT, just fiddly code to improve. For now it > >>> should not be much performane concern. > >>> > >>> I removed hypervisor msgsnd support from patch 3, which is not > >>> required for spapr and added significantly to the patch. > >>> > >>> For now nobody has objected to the way shared SPR access is > >>> handled (serialised with TCG atomics support) so we'll keep > >>> going with it. > >> > >> Cc:ing more people for possible feedback. > >=20 > > Not much feedback so I'll plan to go with this. > >=20 > > A more performant implementation might try to synchronize > > threads at the register level rather than serialize everything, > > but SMT shared registers are not too performance critical so > > this should do for now. > > yes. Could you please rebase this series on upstream ? Oh yeah I should have said, I will rebase and resend. > It would be good to add tests for SMT. May be we could extend : > > tests/avocado/ppc_pseries.py > > with a couple of extra QEMU configs adding 'threads=3D' (if possible) and > check : > > "CPU maps initialized for Y threads per core" > > and > > "smp: Brought up 1 node, X*Y CPUs" > > ? Yeah that could be a good idea, I'll try it. Thanks, Nick