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[14.200.238.131]) by smtp.gmail.com with ESMTPSA id jh13-20020a170903328d00b001b80fe91a40sm649995plb.272.2023.06.26.04.28.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Jun 2023 04:28:57 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 26 Jun 2023 21:28:51 +1000 Message-Id: To: "BALATON Zoltan" , , Cc: , "Greg Kurz" , "Daniel Henrique Barboza" Subject: Re: [PATCH v3 09/14] target/ppc: Move patching nip from exception handler to helper_scv From: "Nicholas Piggin" X-Mailer: aerc 0.15.2 References: In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=npiggin@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri Jun 16, 2023 at 9:03 AM AEST, BALATON Zoltan wrote: > From: Nicholas Piggin > > Unlike sc, for scv a facility unavailable interrupt must be generated > if FSCR[SCV]=3D0 so we can't raise the exception with nip set to next > instruction but we can move advancing nip if the FSCR check passes to > helper_scv so the exception handler does not need to change it. > > [balaton: added commit message] Signed-off-by: Nicholas Piggin Thanks, sorry for the delay :( Would you be able to resend the series? You could drop the machine check one for now perhaps until we sort out what to do with it. Thanks, Nick > Signed-off-by: BALATON Zoltan > --- > This needs SoB from Nick > > target/ppc/excp_helper.c | 2 +- > target/ppc/translate.c | 6 +++++- > 2 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > index 903216c2a6..ef363b0285 100644 > --- a/target/ppc/excp_helper.c > +++ b/target/ppc/excp_helper.c > @@ -1304,7 +1304,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int= excp) > case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception = */ > lev =3D env->error_code; > dump_syscall(env); > - env->nip +=3D 4; > new_msr |=3D env->msr & ((target_ulong)1 << MSR_EE); > new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); > =20 > @@ -2410,6 +2409,7 @@ void helper_ppc_maybe_interrupt(CPUPPCState *env) > void helper_scv(CPUPPCState *env, uint32_t lev) > { > if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) { > + env->nip +=3D 4; > raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev); > } else { > raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV); > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 4260d3d66f..0360a17fb3 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -4433,7 +4433,11 @@ static void gen_scv(DisasContext *ctx) > { > uint32_t lev =3D (ctx->opcode >> 5) & 0x7F; > =20 > - /* Set the PC back to the faulting instruction. */ > + /* > + * Set the PC back to the scv instruction (unlike sc), because a fac= ility > + * unavailable interrupt must be generated if FSCR[SCV]=3D0. The hel= per > + * advances nip if the FSCR check passes. > + */ > gen_update_nip(ctx, ctx->cia); > gen_helper_scv(cpu_env, tcg_constant_i32(lev)); > =20