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[220.244.154.206]) by smtp.gmail.com with ESMTPSA id x48-20020a056a000bf000b0062cf75a9e6bsm37509pfu.131.2023.07.01.01.38.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 01 Jul 2023 01:38:26 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Sat, 01 Jul 2023 18:38:21 +1000 Message-Id: Cc: , "Harsh Prateek Bora" Subject: Re: [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series From: "Nicholas Piggin" To: "Daniel Henrique Barboza" , =?utf-8?q?C=C3=A9dric_Le_Goater?= , X-Mailer: aerc 0.15.2 References: <20230625120317.13877-1-npiggin@gmail.com> <3f70738c-f30a-99a6-6e06-e53b8f93f830@kaod.org> <9989efc7-5ad9-0c31-e0af-b8a735dce353@gmail.com> In-Reply-To: <9989efc7-5ad9-0c31-e0af-b8a735dce353@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sat Jul 1, 2023 at 5:38 AM AEST, Daniel Henrique Barboza wrote: > > > On 6/29/23 01:58, C=C3=A9dric Le Goater wrote: > > On 6/25/23 14:03, Nicholas Piggin wrote: > >> Cedric kindly reviewed these already so I think they should be > >> good to go now. This is just a rebase and slight rewording the > >> changelog. Still haven't completed the main chiptod device yet. > >> > >> Thanks, > >> Nick > >> > >> Nicholas Piggin (2): > >> =C2=A0=C2=A0 target/ppc: Tidy POWER book4 SPR registration > >> =C2=A0=C2=A0 target/ppc: Add TFMR SPR implementation with read and wri= te helpers > >> > >> =C2=A0 target/ppc/cpu_init.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= | 82 ++++++++++++++++++++++++------------ > >> =C2=A0 target/ppc/helper.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 |=C2=A0 2 + > >> =C2=A0 target/ppc/spr_common.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 2= + > >> =C2=A0 target/ppc/timebase_helper.c | 13 ++++++ > >> =C2=A0 target/ppc/translate.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 10= +++++ > >> =C2=A0 5 files changed, 82 insertions(+), 27 deletions(-) > >> > >=20 > >=20 > > Daniel, > >=20 > > When you start building the next PPC PR, I think you can also take > > this patch : > >=20 > > =C2=A0 [4/4] target/ppc: Implement core timebase state machine and TFM= R > > =C2=A0 https://patchwork.ozlabs.org/project/qemu-ppc/patch/20230603233= 612.125879-5-npiggin@gmail.com/ > >=20 > > It belongs to the same series. > > That doesn't apply cleanly with these 2 patches and it didn't look trivia= l to > me. As if there were some code missing. Yeah, it actually uses some signals from the nest chiptod patch. > If Nick re-send it rebased on top of ppc-next I can queue it. Since it's = a > rebase you can keep the r-b. Thanks, I'll see how it goes, it may have to wait for next merge. SMT for powernv is a little more important since it's more user-facing and it would be nice to introduce SMT for both pseries and powernv together. Chiptod for doesn't really do much except step through skiboot init code, and getting more useful things wired up like TB fault / HMI injection won't be ready before freeze. Thanks, Nick