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Iglesias" , "Richard Henderson" , "Greg Kurz" , "Aurelien Jarno" , , "Peter Maydell" , "Daniel Henrique Barboza" , "Aleksandar Rikalo" , "Paolo Bonzini" , "David Gibson" , "Jiaxun Yang" , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Yoshinori Sato" , "Xiaojuan Yang" , Subject: Re: [PATCH 07/12] target/ppc: Use generic hrev64_i64() in BRH / BSWAP16x8 opcodes From: "Nicholas Piggin" To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , X-Mailer: aerc 0.15.2 References: <20230822124042.54739-1-philmd@linaro.org> <20230822125332.55086-1-philmd@linaro.org> In-Reply-To: <20230822125332.55086-1-philmd@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: 83I9zeYHO+2+ On Tue Aug 22, 2023 at 10:53 PM AEST, Philippe Mathieu-Daud=C3=A9 wrote: > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/ppc/translate.c | 10 +--------- > target/ppc/translate/vsx-impl.c.inc | 19 ++----------------- > 2 files changed, 3 insertions(+), 26 deletions(-) > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 74796ec7ba..91a9ec2d1c 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -6435,15 +6435,7 @@ static void gen_brw(DisasContext *ctx) > /* brh */ > static void gen_brh(DisasContext *ctx) > { > - TCGv_i64 mask =3D tcg_constant_i64(0x00ff00ff00ff00ffull); > - TCGv_i64 t1 =3D tcg_temp_new_i64(); > - TCGv_i64 t2 =3D tcg_temp_new_i64(); > - > - tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); > - tcg_gen_and_i64(t2, t1, mask); > - tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); > - tcg_gen_shli_i64(t1, t1, 8); > - tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); > + tcg_gen_hrev64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)= ]); > } > #endif > =20 > diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/v= sx-impl.c.inc > index 0f5b0056f1..639ab7f1bc 100644 > --- a/target/ppc/translate/vsx-impl.c.inc > +++ b/target/ppc/translate/vsx-impl.c.inc > @@ -154,23 +154,8 @@ static void gen_lxvdsx(DisasContext *ctx) > static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl, > TCGv_i64 inh, TCGv_i64 inl) > { > - TCGv_i64 mask =3D tcg_constant_i64(0x00FF00FF00FF00FF); > - TCGv_i64 t0 =3D tcg_temp_new_i64(); > - TCGv_i64 t1 =3D tcg_temp_new_i64(); > - > - /* outh =3D ((inh & mask) << 8) | ((inh >> 8) & mask) */ > - tcg_gen_and_i64(t0, inh, mask); > - tcg_gen_shli_i64(t0, t0, 8); > - tcg_gen_shri_i64(t1, inh, 8); > - tcg_gen_and_i64(t1, t1, mask); > - tcg_gen_or_i64(outh, t0, t1); > - > - /* outl =3D ((inl & mask) << 8) | ((inl >> 8) & mask) */ > - tcg_gen_and_i64(t0, inl, mask); > - tcg_gen_shli_i64(t0, t0, 8); > - tcg_gen_shri_i64(t1, inl, 8); > - tcg_gen_and_i64(t1, t1, mask); > - tcg_gen_or_i64(outl, t0, t1); > + tcg_gen_hrev64_i64(outh, inh); > + tcg_gen_hrev64_i64(outl, inl); > } > =20 > static void gen_bswap32x4(TCGv_i64 outh, TCGv_i64 outl, Reviewed-by: Nicholas Piggin