From: "Luca Weiss" <luca.weiss@fairphone.com>
To: "Doug Anderson" <dianders@chromium.org>
Cc: <cros-qcom-dts-watchers@chromium.org>,
"Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konrad.dybcio@linaro.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Srinivas Kandagatla" <srinivas.kandagatla@linaro.org>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
"Viresh Kumar" <viresh.kumar@linaro.org>,
<~postmarketos/upstreaming@lists.sr.ht>,
<phone-devel@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-gpio@vger.kernel.org>, <linux-pm@vger.kernel.org>
Subject: Re: [PATCH 02/11] nvmem: qfprom: Mark core clk as optional
Date: Fri, 01 Sep 2023 16:54:09 +0200 [thread overview]
Message-ID: <CV7O0TYYEFA8.1Q42JITFSW77Q@otso> (raw)
In-Reply-To: <CAD=FV=XhdORH=naTtoc+kCC4A7UdAJKwq=Te6B3qvXNGBwBieg@mail.gmail.com>
On Wed Aug 30, 2023 at 4:57 PM CEST, Doug Anderson wrote:
> Hi,
>
> On Wed, Aug 30, 2023 at 7:43 AM Luca Weiss <luca.weiss@fairphone.com> wrote:
> >
> > On Wed Aug 30, 2023 at 4:30 PM CEST, Doug Anderson wrote:
> > > Hi,
> > >
> > > On Wed, Aug 30, 2023 at 2:58 AM Luca Weiss <luca.weiss@fairphone.com> wrote:
> > > >
> > > > On some platforms like sc7280 on non-ChromeOS devices the core clock
> > > > cannot be touched by Linux so we cannot provide it. Mark it as optional
> > > > as accessing qfprom works without it.
> > > >
> > > > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > > > ---
> > > > drivers/nvmem/qfprom.c | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > Are you actually testing burning fuses from the OS, or are you just
> > > using the nvmem in "read-only" mode? From comments in the bindings, if
> > > you're trying to burn the fuses then the clock is required. If things
> > > are in read-only mode then the clock isn't required.
> >
> > Hi Doug,
> >
> > I definitely don't plan on burning any fuses on this phone. Not even
> > sure that's allowed by the TZ / boot stack.
> >
> > >
> > > When I compare to the driver, it seems like the driver assumes that if
> > > more than one memory region is provided then you must be supporting
> > > burning fuses. The bindings agree that having 4 memory regions
> > > specified means that the nvmem supports burning and 1 memory region
> > > specified means read-only. The extra 3 memory regions in the nvmem are
> > > all about fuse burning, I believe.
> > >
> > > So maybe the right fix here is to just change your dts to specify one
> > > memory region?
> >
> > I got feedback from Konrad that this here would be the preferred
> > approach compared to having a different dts for ChromeOS vs non-ChromeOS
> > devices. I don't feel strongly to either, for me it's also okay to
> > remove the extra memory regions and only have the main one used on
> > regular qcom devices.
> >
> > Let me know what you think.
>
> I don't hate the idea of leaving the extra memory regions in the dts.
> They do describe the hardware, after all, even if the main OS can't
> actually access those memory regions. ...though the same could also be
> said about the clock you've removed. Said another way: if you want to
> fully describe the hardware then the dts should have the extra memory
> regions and the clock. If you are OK w/ just describing the hardware
> in the way that the OS has access to then the dts should not have the
> extra memory regions and not have the clock. Does that sound right?
Not sure which of those memory regions are actually accessible on this
board, but honestly I don't even want to try accessing it. Blowing fuses
is not my wish there ;)
On downstream the node is just described like the following:
qfprom: qfprom@780000 {
compatible = "qcom,qfprom";
reg = <0x780000 0x7000>;
...
};
So we have 0x780000 - 0x786fff here.
In sc7280.dtsi we have the following:
qfprom: efuse@784000 {
compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
reg = <0 0x00784000 0 0xa20>,
<0 0x00780000 0 0xa20>,
<0 0x00782000 0 0x120>,
<0 0x00786000 0 0x1fff>;
...
};
So I guess this:
* 0x780000 - 0x780a1f
* 0x782000 - 0x78211f
* 0x784000 - 0x784a1f
* 0x786000 - 0x787ffe
So at least the last memory region seems to be partially out of range
according to downstream.
So after reading all of this I tried running this commmand on the phone
and the phone reboots into 900e mode.
$ cat /sys/devices/platform/soc@0/784000.efuse/qfprom0/nvmem
I guess normally this should work? So if I interpret this correctly, the
Linux driver thinks it can access more than it can/should. But also
should probably try this command on another chipset to see if it works
on any really?
Regards
Luca
>
> If somehow you do end up with something like your patch, though,
> you're still missing a bit. Specifically, you don't want to "enable
> writing" a few lines below if you didn't get the clock, right?
>
> -Doug
next prev parent reply other threads:[~2023-09-01 14:54 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-30 9:58 [PATCH 00/11] Initial support for the Fairphone 5 smartphone Luca Weiss
2023-08-30 9:58 ` [PATCH 01/11] arm64: dts: qcom: sc7280: Mark some nodes as 'reserved' Luca Weiss
2023-08-30 10:08 ` Konrad Dybcio
2023-08-30 10:35 ` Luca Weiss
2023-08-30 10:45 ` Konrad Dybcio
2023-08-30 9:58 ` [PATCH 02/11] nvmem: qfprom: Mark core clk as optional Luca Weiss
2023-08-30 10:03 ` Krzysztof Kozlowski
2023-08-30 14:30 ` Doug Anderson
2023-08-30 14:43 ` Luca Weiss
2023-08-30 14:57 ` Doug Anderson
2023-09-01 14:54 ` Luca Weiss [this message]
2023-09-01 15:08 ` Doug Anderson
2023-09-02 11:28 ` Konrad Dybcio
2023-09-04 8:14 ` Luca Weiss
2023-09-01 20:29 ` Trilok Soni
2023-08-30 9:58 ` [PATCH 03/11] arm64: dts: qcom: sc7280: Move qfprom clock to chrome-common Luca Weiss
2023-08-30 10:09 ` Konrad Dybcio
2023-08-31 11:28 ` Luca Weiss
2023-08-30 9:58 ` [PATCH 04/11] arm64: dts: qcom: pm7250b: make SID configurable Luca Weiss
2023-08-30 10:06 ` Krzysztof Kozlowski
2023-08-31 10:12 ` Luca Weiss
2023-08-31 11:33 ` Dmitry Baryshkov
2023-08-31 11:54 ` Krzysztof Kozlowski
2023-08-31 12:27 ` Dmitry Baryshkov
2023-09-05 8:30 ` Luca Weiss
2023-09-11 8:34 ` Luca Weiss
2023-09-11 9:44 ` Krzysztof Kozlowski
2023-09-11 9:59 ` Luca Weiss
2023-09-11 11:15 ` Krzysztof Kozlowski
2023-09-11 11:22 ` Konrad Dybcio
2023-08-31 12:32 ` Luca Weiss
2023-08-30 9:58 ` [PATCH 05/11] arm64: dts: qcom: pm8350c: Add flash led node Luca Weiss
2023-08-30 9:58 ` [PATCH 06/11] dt-bindings: pinctrl: qcom,sc7280: Allow gpio-reserved-ranges Luca Weiss
2023-08-30 10:08 ` Krzysztof Kozlowski
2023-08-30 11:47 ` Linus Walleij
2023-08-30 9:58 ` [PATCH 07/11] dt-bindings: arm: qcom,ids: Add SoC ID for QCM6490 Luca Weiss
2023-08-30 10:08 ` Krzysztof Kozlowski
2023-08-30 10:16 ` Konrad Dybcio
2023-08-30 9:58 ` [PATCH 08/11] soc: qcom: socinfo: " Luca Weiss
2023-08-30 10:09 ` Krzysztof Kozlowski
2023-08-30 9:58 ` [PATCH 09/11] cpufreq: Add QCM6490 to cpufreq-dt-platdev blocklist Luca Weiss
2023-08-30 10:10 ` Krzysztof Kozlowski
2023-08-31 5:01 ` Viresh Kumar
2023-08-30 9:58 ` [PATCH 10/11] dt-bindings: arm: qcom: Add QCM6490 Fairphone 5 Luca Weiss
2023-08-30 10:13 ` Krzysztof Kozlowski
2023-08-30 9:58 ` [PATCH 11/11] arm64: dts: qcom: qcm6490: Add device-tree for " Luca Weiss
2023-08-30 10:17 ` Krzysztof Kozlowski
2023-08-30 10:45 ` Konrad Dybcio
2023-09-01 14:27 ` Luca Weiss
2023-09-02 11:45 ` Konrad Dybcio
2023-09-04 8:19 ` Luca Weiss
2023-09-14 16:04 ` (subset) [PATCH 00/11] Initial support for the Fairphone 5 smartphone Bjorn Andersson
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