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[110.175.163.154]) by smtp.gmail.com with ESMTPSA id w16-20020aa79a10000000b006e4362d0d8csm5072501pfj.36.2024.02.26.22.24.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Feb 2024 22:24:03 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 27 Feb 2024 16:23:59 +1000 Message-Id: Cc: "Daniel Henrique Barboza" , Subject: Re: [PATCH v6 3/9] target/ppc: Fix gen_sc to use correct nip From: "Nicholas Piggin" To: "BALATON Zoltan" , , X-Mailer: aerc 0.15.2 References: <9bb0926a0e9f3b5c703fe0b4b6d21edd8eb79bdd.1708601065.git.balaton@eik.bme.hu> In-Reply-To: <9bb0926a0e9f3b5c703fe0b4b6d21edd8eb79bdd.1708601065.git.balaton@eik.bme.hu> Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=npiggin@gmail.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu Feb 22, 2024 at 9:33 PM AEST, BALATON Zoltan wrote: > Most exceptions are raised with nip pointing to the faulting > instruction but the sc instruction generating a syscall exception > leaves nip pointing to next instruction. Fix gen_sc to not use > gen_exception_err() which sets nip back but correctly set nip to > pc_next so we don't have to patch this in the exception handlers. > > Signed-off-by: BALATON Zoltan > Reviewed-by: Nicholas Piggin Mixed feelings about this one still but I suppose I will add it now you have the tracing corrected. Although one more thing: > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 049f636927..6a43eda3b9 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -4535,15 +4535,17 @@ static void gen_hrfid(DisasContext *ctx) > #endif > static void gen_sc(DisasContext *ctx) > { > - uint32_t lev; > - > /* > * LEV is a 7-bit field, but the top 6 bits are treated as a reserve= d > * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that = is > * for Ultravisor which TCG does not support, so just ignore the top= 6. > */ > - lev =3D (ctx->opcode >> 5) & 0x1; > - gen_exception_err(ctx, POWERPC_SYSCALL, lev); > + uint32_t lev =3D (ctx->opcode >> 5) & 0x1; > + > + gen_update_nip(ctx, ctx->base.pc_next); > + gen_helper_raise_exception_err(tcg_env, tcg_constant_i32(POWERPC_SYS= CALL), > + tcg_constant_i32(lev)); > + ctx->base.is_jmp =3D DISAS_NORETURN; > } > =20 > #if defined(TARGET_PPC64) Can you share this code with gen_exception_err, by making gen_exception_err_nip that takes the nip? Thanks, Nick