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[82.122.123.137]) by smtp.gmail.com with ESMTPSA id wm18-20020a05620a581200b00787e1e94d00sm683328qkn.109.2024.02.29.05.56.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Feb 2024 05:56:45 -0800 (PST) Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 29 Feb 2024 14:56:41 +0100 Message-Id: Subject: Re: [PATCH v2 13/14] pinctrl: pinctrl-tps6594: Add TPS65224 PMIC pinctrl and GPIO From: "Esteban Blanc" To: "Bhargav Raviprakash" , Cc: , , , , , , , , , , , , , , , , X-Mailer: aerc 0.17.0 References: <20240223093701.66034-1-bhargav.r@ltts.com> <20240223093701.66034-14-bhargav.r@ltts.com> In-Reply-To: <20240223093701.66034-14-bhargav.r@ltts.com> On Fri Feb 23, 2024 at 10:37 AM CET, Bhargav Raviprakash wrote: > From: Nirmala Devi Mal Nadar > > Add support for TPS65224 pinctrl and GPIOs to TPS6594 driver as they > have significant functional overlap. > TPS65224 PMIC has 6 GPIOS which can be configured as GPIO or other > dedicated device functions. > > Signed-off-by: Nirmala Devi Mal Nadar > Signed-off-by: Bhargav Raviprakash > --- > drivers/pinctrl/pinctrl-tps6594.c | 287 +++++++++++++++++++++++++----- > 1 file changed, 246 insertions(+), 41 deletions(-) > > diff --git a/drivers/pinctrl/pinctrl-tps6594.c b/drivers/pinctrl/pinctrl-= tps6594.c > index 66985e54b..5da21aa14 100644 > --- a/drivers/pinctrl/pinctrl-tps6594.c > +++ b/drivers/pinctrl/pinctrl-tps6594.c > @@ -201,7 +319,21 @@ static int tps6594_gpio_regmap_xlate(struct gpio_reg= map *gpio, > =20 > static int tps6594_pmx_func_cnt(struct pinctrl_dev *pctldev) > { > - return ARRAY_SIZE(pinctrl_functions); > + struct tps6594_pinctrl *pinctrl =3D pinctrl_dev_get_drvdata(pctldev); > + int func_cnt =3D 0; > + > + switch (pinctrl->tps->chip_id) { See below. > @@ -229,10 +361,26 @@ static int tps6594_pmx_set(struct tps6594_pinctrl *= pinctrl, unsigned int pin, > u8 muxval) > { > u8 mux_sel_val =3D muxval << TPS6594_OFFSET_GPIO_SEL; > + u8 mux_sel_mask =3D 0; > + > + switch (pinctrl->tps->chip_id) { See below. > @@ -240,16 +388,28 @@ static int tps6594_pmx_set_mux(struct pinctrl_dev *= pctldev, > { > struct tps6594_pinctrl *pinctrl =3D pinctrl_dev_get_drvdata(pctldev); > u8 muxval =3D pinctrl->funcs[function].muxval; > + unsigned int remap_cnt =3D 0; > + struct muxval_remap *remap; > =20 > /* Some pins don't have the same muxval for the same function... */ > - if (group =3D=3D 8) { > - if (muxval =3D=3D TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION) > - muxval =3D TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION_GPIO8; > - else if (muxval =3D=3D TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION) > - muxval =3D TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION_GPIO8; > - } else if (group =3D=3D 9) { > - if (muxval =3D=3D TPS6594_PINCTRL_CLK32KOUT_FUNCTION) > - muxval =3D TPS6594_PINCTRL_CLK32KOUT_FUNCTION_GPIO9; > + switch (pinctrl->tps->chip_id) { See below. > @@ -276,7 +436,21 @@ static const struct pinmux_ops tps6594_pmx_ops =3D { > =20 > static int tps6594_groups_cnt(struct pinctrl_dev *pctldev) > { > - return ARRAY_SIZE(tps6594_pins); > + struct tps6594_pinctrl *pinctrl =3D pinctrl_dev_get_drvdata(pctldev); > + int num_pins =3D 0; > + > + switch (pinctrl->tps->chip_id) { See below. > @@ -320,8 +494,18 @@ static int tps6594_pinctrl_probe(struct platform_dev= ice *pdev) > return -ENOMEM; > pctrl_desc->name =3D dev_name(dev); > pctrl_desc->owner =3D THIS_MODULE; > - pctrl_desc->pins =3D tps6594_pins; > - pctrl_desc->npins =3D ARRAY_SIZE(tps6594_pins); > + switch (tps->chip_id) { See below. > @@ -329,8 +513,18 @@ static int tps6594_pinctrl_probe(struct platform_dev= ice *pdev) > if (!pinctrl) > return -ENOMEM; > pinctrl->tps =3D dev_get_drvdata(dev->parent); > - pinctrl->funcs =3D pinctrl_functions; > - pinctrl->pins =3D tps6594_pins; > + switch (pinctrl->tps->chip_id) { See below. > @@ -338,8 +532,18 @@ static int tps6594_pinctrl_probe(struct platform_dev= ice *pdev) > =20 > config.parent =3D tps->dev; > config.regmap =3D tps->regmap; > - config.ngpio =3D TPS6594_PINCTRL_PINS_NB; > - config.ngpio_per_reg =3D 8; > + switch (pinctrl->tps->chip_id) { Regarding all the switch case, I think you should try and put all the differences inside the `struct tps6594_pinctrl`. This way most of the functions (if not all of them) could be writen without the switch case, making them more readable and straight forward to understand. You already have some switch case in the probe, why not fill the `struct tps6594_pintcl` there and use these new fileds in the different function. It's not pretty today, imagine if in the future there is more supported chip, it would be quite unreadable IMAO. Other than that the changes looks fine to me. I will have to boot a board with TPS6594 to check that whole series did not break anything. Please add me to your Cc for the next round. Best regards, --=20 Esteban "Skallwar" Blanc BayLibre From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8374C48BF6 for ; Thu, 29 Feb 2024 13:57:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:References:Cc:To:From: Subject:Message-Id:Date:Mime-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/7fJUTYbuPriBO8DcBxKG4pCnCSJ5GLpe+yAqOtoQ2w=; b=hRhcOE/hh3L+Vn /miLPUldiR6tSRIRldtoGEHolhwDjkv1Cj1I1jul2yv/Drwrqs+GfdQ8i+Tgj/Q+6CpNUbPCnrpGX 90USDflmECzg5Y1YAo2b7WQoXiM4a5UxMj8kwQHNpdp+WmfhqSTcdKmCwNpEmWG9iRUUwn0xH/Ym0 uJGlV+S5bI6FyvjUqIHTMUZdcMuPZ5GIyM7LUpPLYcaajOsx3UTFc6b7pryZHdXVB7Sppk9EVUg4l MY98P+q5odd2AWBqTebzaOKA+grys0T7F1LnSxhvcH3Vu4uS7Xbf4TQIXqcbnWzuCddHmVTSJIZ35 CVILyp9Cjdy2MzT8eFZw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rfgu3-0000000DlDW-0f9q; Thu, 29 Feb 2024 13:56:51 +0000 Received: from mail-qt1-x835.google.com ([2607:f8b0:4864:20::835]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rfgtz-0000000DlD2-42Qb for linux-arm-kernel@lists.infradead.org; Thu, 29 Feb 2024 13:56:49 +0000 Received: by mail-qt1-x835.google.com with SMTP id d75a77b69052e-42e7ed64b5fso3040231cf.1 for ; Thu, 29 Feb 2024 05:56:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1709215006; x=1709819806; darn=lists.infradead.org; h=in-reply-to:references:cc:to:from:subject:message-id:date :content-transfer-encoding:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=UNhdXSdXkLjYVE0deMxEiGlQYDwDvXw88ZjC208fOao=; b=cjOhc4wnjCJSPRs3lQ5kSAuwP8Uu0kc8Gu9Z80/DS334k5SLpZbhwtDXvnVSBPSyJM T9PypbAn6N5z2KCTnvxZRiIeCRvKVO0sd9pQsUIRX9TWFg4k5X5KmIYGe4y6+by5N4OA CqBN6CwAvhUkvJQOASxbi7mGng5A6kAd5X9eDBO9BiOd9OYP93WGADQJ+/e8CMkePH0k QATr2PtxU9ds3G37JaHkd3Xccm3l+43Agtvcr3AXw13eUk08G3E00PxuO5nOw1aSqib3 Lh3zz4tcWQFXJDmAkCfmOfuHCDwpyAOEV8pm43+0wlFocclH31LPCxawwDB526V+7R/8 IRIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709215006; x=1709819806; h=in-reply-to:references:cc:to:from:subject:message-id:date :content-transfer-encoding:mime-version:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=UNhdXSdXkLjYVE0deMxEiGlQYDwDvXw88ZjC208fOao=; b=fRNQvVWvYRllypkuojKWW0pR2aqfz3MzddLmR9ZZfJEckbhwd7DWHyHAwAbxvMLv4G rvVyYaLK/sJ8Ul/IlB6PQdpZCX42krAhjfjZ7HDseIv65Tv2MW9FcN7m9FxdNpiArSDW HNJosDjo9V3WshXizMUUr+Abb2++BlFvvBedAuxy6q0cLYZJQczVr9TJ4924pjpoVFZU 8HxBRgVQrJy1pqp6pZj8/3Ag1s5jViQZx7K52x+RnyxKv3oBAbPtIlVHzlA0uJ7j8W4w av2gTqLw8jb3Fr5zsRBU63UPkBFHuBbA4oTCW32XveFU8bMxIOmwB+iiroXNqW+Hf9ln qSQA== X-Forwarded-Encrypted: i=1; AJvYcCU0ZjufhwDv9tvOb3+qqVmxx4nz7trjNSx2yBHQGjoYQgyKWad4nJRFEprG7zlNa0ydO+fJ0+11BJ+0Fg2e/dvtyViPV08wQlg8hNS9ocFn0zMhQYU= X-Gm-Message-State: AOJu0Yx0DZ3ZhnO85wrAfpROv0k5jxdG+sfXzkUl/m1q5ks+O+h43S64 6JWwWg8L5iw91UXRRNQOdAWMCIzn+NdStCLta4hFmWc8QcvPaQAWe7oImG2oki8= X-Google-Smtp-Source: AGHT+IEBTojVUp8KOWJFuGjpZRNuTCVqmMqtQlVhuYYbIVXRAFqeFqc1mPKHL93Sf9q9YMhtXSG3EQ== X-Received: by 2002:ac8:7ca:0:b0:42e:b8d1:2b2a with SMTP id m10-20020ac807ca000000b0042eb8d12b2amr1769677qth.48.1709215005911; Thu, 29 Feb 2024 05:56:45 -0800 (PST) Received: from localhost (alyon-651-1-22-137.w82-122.abo.wanadoo.fr. [82.122.123.137]) by smtp.gmail.com with ESMTPSA id wm18-20020a05620a581200b00787e1e94d00sm683328qkn.109.2024.02.29.05.56.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Feb 2024 05:56:45 -0800 (PST) Mime-Version: 1.0 Date: Thu, 29 Feb 2024 14:56:41 +0100 Message-Id: Subject: Re: [PATCH v2 13/14] pinctrl: pinctrl-tps6594: Add TPS65224 PMIC pinctrl and GPIO From: "Esteban Blanc" To: "Bhargav Raviprakash" , Cc: , , , , , , , , , , , , , , , , X-Mailer: aerc 0.17.0 References: <20240223093701.66034-1-bhargav.r@ltts.com> <20240223093701.66034-14-bhargav.r@ltts.com> In-Reply-To: <20240223093701.66034-14-bhargav.r@ltts.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240229_055648_298192_D9C1883C X-CRM114-Status: GOOD ( 25.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri Feb 23, 2024 at 10:37 AM CET, Bhargav Raviprakash wrote: > From: Nirmala Devi Mal Nadar > > Add support for TPS65224 pinctrl and GPIOs to TPS6594 driver as they > have significant functional overlap. > TPS65224 PMIC has 6 GPIOS which can be configured as GPIO or other > dedicated device functions. > > Signed-off-by: Nirmala Devi Mal Nadar > Signed-off-by: Bhargav Raviprakash > --- > drivers/pinctrl/pinctrl-tps6594.c | 287 +++++++++++++++++++++++++----- > 1 file changed, 246 insertions(+), 41 deletions(-) > > diff --git a/drivers/pinctrl/pinctrl-tps6594.c b/drivers/pinctrl/pinctrl-tps6594.c > index 66985e54b..5da21aa14 100644 > --- a/drivers/pinctrl/pinctrl-tps6594.c > +++ b/drivers/pinctrl/pinctrl-tps6594.c > @@ -201,7 +319,21 @@ static int tps6594_gpio_regmap_xlate(struct gpio_regmap *gpio, > > static int tps6594_pmx_func_cnt(struct pinctrl_dev *pctldev) > { > - return ARRAY_SIZE(pinctrl_functions); > + struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); > + int func_cnt = 0; > + > + switch (pinctrl->tps->chip_id) { See below. > @@ -229,10 +361,26 @@ static int tps6594_pmx_set(struct tps6594_pinctrl *pinctrl, unsigned int pin, > u8 muxval) > { > u8 mux_sel_val = muxval << TPS6594_OFFSET_GPIO_SEL; > + u8 mux_sel_mask = 0; > + > + switch (pinctrl->tps->chip_id) { See below. > @@ -240,16 +388,28 @@ static int tps6594_pmx_set_mux(struct pinctrl_dev *pctldev, > { > struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); > u8 muxval = pinctrl->funcs[function].muxval; > + unsigned int remap_cnt = 0; > + struct muxval_remap *remap; > > /* Some pins don't have the same muxval for the same function... */ > - if (group == 8) { > - if (muxval == TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION) > - muxval = TPS6594_PINCTRL_DISABLE_WDOG_FUNCTION_GPIO8; > - else if (muxval == TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION) > - muxval = TPS6594_PINCTRL_SYNCCLKOUT_FUNCTION_GPIO8; > - } else if (group == 9) { > - if (muxval == TPS6594_PINCTRL_CLK32KOUT_FUNCTION) > - muxval = TPS6594_PINCTRL_CLK32KOUT_FUNCTION_GPIO9; > + switch (pinctrl->tps->chip_id) { See below. > @@ -276,7 +436,21 @@ static const struct pinmux_ops tps6594_pmx_ops = { > > static int tps6594_groups_cnt(struct pinctrl_dev *pctldev) > { > - return ARRAY_SIZE(tps6594_pins); > + struct tps6594_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); > + int num_pins = 0; > + > + switch (pinctrl->tps->chip_id) { See below. > @@ -320,8 +494,18 @@ static int tps6594_pinctrl_probe(struct platform_device *pdev) > return -ENOMEM; > pctrl_desc->name = dev_name(dev); > pctrl_desc->owner = THIS_MODULE; > - pctrl_desc->pins = tps6594_pins; > - pctrl_desc->npins = ARRAY_SIZE(tps6594_pins); > + switch (tps->chip_id) { See below. > @@ -329,8 +513,18 @@ static int tps6594_pinctrl_probe(struct platform_device *pdev) > if (!pinctrl) > return -ENOMEM; > pinctrl->tps = dev_get_drvdata(dev->parent); > - pinctrl->funcs = pinctrl_functions; > - pinctrl->pins = tps6594_pins; > + switch (pinctrl->tps->chip_id) { See below. > @@ -338,8 +532,18 @@ static int tps6594_pinctrl_probe(struct platform_device *pdev) > > config.parent = tps->dev; > config.regmap = tps->regmap; > - config.ngpio = TPS6594_PINCTRL_PINS_NB; > - config.ngpio_per_reg = 8; > + switch (pinctrl->tps->chip_id) { Regarding all the switch case, I think you should try and put all the differences inside the `struct tps6594_pinctrl`. This way most of the functions (if not all of them) could be writen without the switch case, making them more readable and straight forward to understand. You already have some switch case in the probe, why not fill the `struct tps6594_pintcl` there and use these new fileds in the different function. It's not pretty today, imagine if in the future there is more supported chip, it would be quite unreadable IMAO. Other than that the changes looks fine to me. I will have to boot a board with TPS6594 to check that whole series did not break anything. Please add me to your Cc for the next round. Best regards, -- Esteban "Skallwar" Blanc BayLibre _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel