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Tue, 12 Mar 2024 01:55:53 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 12 Mar 2024 18:55:48 +1000 Message-Id: From: "Nicholas Piggin" To: "Harsh Prateek Bora" , Cc: , "Daniel Henrique Barboza" , "David Gibson" Subject: Re: [PATCH 02/13] target/ppc: POWER10 does not have transactional memory X-Mailer: aerc 0.15.2 References: <20240311185200.2185753-1-npiggin@gmail.com> <20240311185200.2185753-3-npiggin@gmail.com> In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::c35; envelope-from=npiggin@gmail.com; helo=mail-oo1-xc35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue Mar 12, 2024 at 6:10 PM AEST, Harsh Prateek Bora wrote: > Hi Nick, > > One query/comment below: > > On 3/12/24 00:21, Nicholas Piggin wrote: > > POWER10 hardware implements a degenerate transactional memory facility > > in POWER8/9 PCR compatibility modes to permit migration from older > > CPUs, but POWER10 / ISA v3.1 mode does not support it so the CPU model > > should not support it. > >=20 > > Signed-off-by: Nicholas Piggin > > --- > > target/ppc/cpu_init.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > >=20 > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > > index 572cbdf25f..d7e84a2f40 100644 > > --- a/target/ppc/cpu_init.c > > +++ b/target/ppc/cpu_init.c > > @@ -6573,7 +6573,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *da= ta) > > PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | > > PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | > > PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 = | > > - PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA= 310 | > > + PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | > > PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; > > pcc->msr_mask =3D (1ull << MSR_SF) | > > (1ull << MSR_HV) | > > @@ -6617,7 +6617,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *da= ta) > > pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | > > POWERPC_FLAG_BE | POWERPC_FLAG_PMM | > > POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | > > - POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV= ; > > + POWERPC_FLAG_VSX | POWERPC_FLAG_SCV; > > pcc->l1_dcache_size =3D 0x8000; > > pcc->l1_icache_size =3D 0x8000; > > } > > Shouldn't we also have below change included with this: > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index aac095e5fd..faefc0420e 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6641,7 +6641,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data= ) > PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206 | PPC2_ATTN; > pcc->msr_mask =3D (1ull << MSR_SF) | > (1ull << MSR_HV) | > - (1ull << MSR_TM) | > (1ull << MSR_VR) | > (1ull << MSR_VSX) | > (1ull << MSR_EE) | I think you're probably right. I'll do some testing... Thanks, Nick > > Otherwise, > Reviewed-by: Harsh Prateek Bora