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[193.116.208.39]) by smtp.gmail.com with ESMTPSA id ey1-20020a056a0038c100b006e6b12d650asm10675761pfb.31.2024.03.19.22.00.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Mar 2024 22:00:47 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 20 Mar 2024 15:00:42 +1000 Message-Id: Cc: , "Richard Henderson" , , , , "Anton Johansson" , "Daniel Henrique Barboza" Subject: Re: [PATCH-for-9.1 18/27] target/ppc: Convert to TCGCPUOps::get_cpu_state() From: "Nicholas Piggin" To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , X-Mailer: aerc 0.15.2 References: <20240319154258.71206-1-philmd@linaro.org> <20240319154258.71206-19-philmd@linaro.org> In-Reply-To: <20240319154258.71206-19-philmd@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=npiggin@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Wed Mar 20, 2024 at 1:42 AM AEST, Philippe Mathieu-Daud=C3=A9 wrote: > Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state(), > unifying with the method declared in target/ppc/helper_regs.c. Looks okay AFAIKS. Reviewed-by: Nicholas Piggin > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/ppc/cpu.h | 16 +++------------- > target/ppc/cpu_init.c | 1 + > target/ppc/helper_regs.c | 13 +++++++------ > 3 files changed, 11 insertions(+), 19 deletions(-) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index ced4e53024..6aa18db335 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -2716,19 +2716,9 @@ void cpu_write_xer(CPUPPCState *env, target_ulong = xer); > */ > #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) > =20 > -#define TARGET_HAS_CPU_GET_TB_CPU_STATE > - > -#ifdef CONFIG_DEBUG_TCG > -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, > - uint64_t *cs_base, uint32_t *flags); > -#else > -static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, > - uint64_t *cs_base, uint32_t *fla= gs) > -{ > - *pc =3D env->nip; > - *cs_base =3D 0; > - *flags =3D env->hflags; > -} > +#ifdef CONFIG_TCG > +void ppc_get_cpu_state(CPUPPCState *env, vaddr *pc, > + uint64_t *cs_base, uint32_t *flags); > #endif > =20 > G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception); > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 464e91faa2..673559b444 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -7362,6 +7362,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D= { > static const TCGCPUOps ppc_tcg_ops =3D { > .initialize =3D ppc_translate_init, > .restore_state_to_opc =3D ppc_restore_state_to_opc, > + .get_cpu_state =3D ppc_get_cpu_state, > =20 > #ifdef CONFIG_USER_ONLY > .record_sigsegv =3D ppc_cpu_record_sigsegv, > diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c > index 25258986e3..e62591067c 100644 > --- a/target/ppc/helper_regs.c > +++ b/target/ppc/helper_regs.c > @@ -217,25 +217,26 @@ void hreg_update_pmu_hflags(CPUPPCState *env) > env->hflags |=3D hreg_compute_pmu_hflags_value(env); > } > =20 > -#ifdef CONFIG_DEBUG_TCG > -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, > - uint64_t *cs_base, uint32_t *flags) > +#ifdef CONFIG_TCG > +void ppc_get_cpu_state(CPUPPCState *env, vaddr *pc, > + uint64_t *cs_base, uint32_t *flags) > { > uint32_t hflags_current =3D env->hflags; > - uint32_t hflags_rebuilt; > =20 > *pc =3D env->nip; > *cs_base =3D 0; > *flags =3D hflags_current; > =20 > - hflags_rebuilt =3D hreg_compute_hflags_value(env); > +#ifdef CONFIG_DEBUG_TCG > + uint32_t hflags_rebuilt =3D hreg_compute_hflags_value(env); > if (unlikely(hflags_current !=3D hflags_rebuilt)) { > cpu_abort(env_cpu(env), > "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n= ", > hflags_current, hflags_rebuilt); > } > -} > #endif > +} > +#endif /* CONFIG_TCG */ > =20 > void cpu_interrupt_exittb(CPUState *cs) > {