From: "Nicholas Piggin" <npiggin@gmail.com>
To: "Richard Henderson" <richard.henderson@linaro.org>,
<qemu-ppc@nongnu.org>
Cc: <qemu-devel@nongnu.org>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Glenn Miles" <milesg@linux.vnet.ibm.com>,
"Chinmay Rath" <rathc@linux.ibm.com>
Subject: Re: [PATCH v2 03/12] target/ppc: Implement attn instruction on BookS 64-bit processors
Date: Wed, 22 May 2024 11:32:49 +1000 [thread overview]
Message-ID: <D1FSB461VH13.339I0W6KA470U@gmail.com> (raw)
In-Reply-To: <f407d5ba-2405-4723-bf86-dacdb7cf9a91@linaro.org>
On Wed May 22, 2024 at 3:34 AM AEST, Richard Henderson wrote:
> On 5/20/24 18:30, Nicholas Piggin wrote:
> > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> > index c358927211..2532408be0 100644
> > --- a/target/ppc/cpu.h
> > +++ b/target/ppc/cpu.h
> > @@ -3025,6 +3031,12 @@ static inline int check_pow_nocheck(CPUPPCState *env)
> > return 1;
> > }
> >
> > +/* attn enable check */
> > +static inline int check_attn_none(CPUPPCState *env)
> > +{
> > + return 0;
> > +}
>
> No point in putting this here, as a static inline...
>
> > @@ -2138,6 +2158,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
> > dc->desc = "PowerPC 405";
> > pcc->init_proc = init_proc_405;
> > pcc->check_pow = check_pow_nocheck;
> > + pcc->check_attn = check_attn_none;
>
> ... when the only uses force an out-of-line instance.
Yeah... I was following existing convention (although apparently not
naming convention :/).
>
> Alternately,
>
> > +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> > +void helper_attn(CPUPPCState *env)
> > +{
> > + /* POWER attn is unprivileged when enabled by HID, otherwise illegal */
> > + if ((*env->check_attn)(env)) {
> > + powerpc_checkstop(env, "host executed attn");
>
> ... allow the hook to be null to indicate no attn.
I'll add a todo list to change this and check_pow to follow this
suggestion.
>
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Thanks,
Nick
next prev parent reply other threads:[~2024-05-22 1:33 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-21 1:30 [PATCH v2 00/12] target/ppc: Various TCG emulation patches Nicholas Piggin
2024-05-21 1:30 ` [PATCH v2 01/12] target/ppc: Make checkstop actually stop the system Nicholas Piggin
2024-05-21 15:32 ` Miles Glenn
2024-05-21 1:30 ` [PATCH v2 02/12] target/ppc: improve checkstop logging Nicholas Piggin
2024-05-21 15:37 ` Miles Glenn
2024-05-21 17:29 ` Richard Henderson
2025-04-29 6:49 ` Philippe Mathieu-Daudé
2024-05-21 1:30 ` [PATCH v2 03/12] target/ppc: Implement attn instruction on BookS 64-bit processors Nicholas Piggin
2024-05-21 15:41 ` Miles Glenn
2024-05-22 1:30 ` Nicholas Piggin
2024-05-21 17:34 ` Richard Henderson
2024-05-22 1:32 ` Nicholas Piggin [this message]
2024-05-21 1:30 ` [PATCH v2 04/12] target/ppc: BookE DECAR SPR is 32-bit Nicholas Piggin
2024-05-21 15:44 ` Miles Glenn
2024-05-21 1:30 ` [PATCH v2 05/12] target/ppc: Wire up BookE ATB registers for e500 family Nicholas Piggin
2024-05-21 1:30 ` [PATCH v2 06/12] target/ppc: Add PPR32 SPR Nicholas Piggin
2024-05-21 15:52 ` Miles Glenn
2024-05-21 17:40 ` Richard Henderson
2024-05-22 1:43 ` Nicholas Piggin
2024-05-21 1:30 ` [PATCH v2 07/12] target/ppc: add helper to write per-LPAR SPRs Nicholas Piggin
2024-05-21 16:50 ` Miles Glenn
2024-05-21 1:30 ` [PATCH v2 08/12] target/ppc: Add SMT support to simple SPRs Nicholas Piggin
2024-05-21 15:56 ` Miles Glenn
2024-05-21 1:30 ` [PATCH v2 09/12] target/ppc: Add SMT support to PTCR SPR Nicholas Piggin
2024-05-21 16:02 ` Miles Glenn
2024-05-21 1:30 ` [PATCH v2 10/12] target/ppc: Implement LDBAR, TTR SPRs Nicholas Piggin
2024-05-21 16:41 ` Miles Glenn
2024-05-21 1:30 ` [PATCH v2 11/12] target/ppc: Implement SPRC/SPRD SPRs Nicholas Piggin
2024-05-21 16:37 ` Miles Glenn
2024-05-21 1:30 ` [PATCH v2 12/12] target/ppc: add SMT support to msgsnd broadcast Nicholas Piggin
2024-05-21 17:07 ` Miles Glenn
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