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[110.175.65.7]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0c136a12sm228490755ad.251.2024.05.21.18.43.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 May 2024 18:43:07 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 22 May 2024 11:43:02 +1000 Message-Id: Subject: Re: [PATCH v2 06/12] target/ppc: Add PPR32 SPR From: "Nicholas Piggin" To: "Richard Henderson" , Cc: , "Daniel Henrique Barboza" , "Glenn Miles" , "Chinmay Rath" X-Mailer: aerc 0.17.0 References: <20240521013029.30082-1-npiggin@gmail.com> <20240521013029.30082-7-npiggin@gmail.com> <05148488-d827-4c6a-936b-5eeaff2a5d86@linaro.org> In-Reply-To: <05148488-d827-4c6a-936b-5eeaff2a5d86@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed May 22, 2024 at 3:40 AM AEST, Richard Henderson wrote: > On 5/20/24 18:30, Nicholas Piggin wrote: > > +void spr_write_ppr32(DisasContext *ctx, int sprn, int gprn) > > +{ > > + TCGv t0 =3D tcg_temp_new(); > > + > > + tcg_gen_shli_tl(t0, cpu_gpr[gprn], 32); > > + gen_store_spr(SPR_PPR, t0); > > + spr_store_dump_spr(SPR_PPR); > > +} > > The documentation isn't clear on whether this zaps the low 32 bits. If th= e low bits of PPR=20 > are {reserved, must-be-zero, undefined} or suchlike, this is fine. > > If not, then you need a deposit here, to preserve those bits, e.g.: > > gen_load_spr(t0, SPR_PPR); > tcg_gen_deposit_tl(t0, t0, cpu_gpr[gprn], 32, 32); > gen_store_spr(SPR_PPR, t0); > > Anyway, it might be best to add a comment here re the above. Oh good catch. The other bits are reserved which means they can return 0 but it's not necessary. We implement all the bits though, so we should not have mtPPR32 zeroing out the other half. In theory we probably can since they're "undefined", but it doesn't seem nice. Actually now I look the ISA says reserved bits in SPRs should return 0 for reads in user-mode which we get wrong in a few places. Anyway yes, for now I'll go with your deposit. Thank you. Thanks, Nick