Re: [PATCH V2] staging: nvec: make i2c controller register writes robust

["Thierry Reding" <thierry.reding@gmail.com>]

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On Sun May 26, 2024 at 9:39 PM CEST, Marc Dietrich wrote:
> The i2c controller needs to read back the data written to its registers.
> This way we can avoid the long delay in the interrupt handler.
>
> Signed-off-by: Marc Dietrich <marvin24@gmx.de>
> ---
> V2: rename i2c_writel to tegra_i2c_writel
>  drivers/staging/nvec/nvec.c | 41 ++++++++++++++++++++++---------------
>  1 file changed, 24 insertions(+), 17 deletions(-)

Hi Marc,

I've been trying to find out why we need to do these register read backs
and so far I haven't found anything tangible. The only thing I was able
to find that sounds like it could be remotely related to this is a
mention of the interface clock being fixed at 72 MHz. So I'm wondering
if you could perhaps verify in your setup what the I2C module clock is
for the NVEC controller (any dump of the clk_summary debugfs file after
boot would do).

Since I'm not sure we'll get to the bottom of this, this looks clean and
is certainly an improvement over the udelay(100), so:

Reviewed-by: Thierry Reding <treding@nvidia.com>

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