Re: [PATCH v2 4/7] target/ppc: optimize p9 exception handling routines

["Nicholas Piggin" <npiggin@gmail.com>]

On Thu May 23, 2024 at 3:14 PM AEST, Harsh Prateek Bora wrote:
> Currently, p9 exception handling has multiple if-condition checks where
> it does an indirect access to pending_interrupts via env. Pass the
> value during entry to avoid multiple indirect accesses.

Does code change? I don't mind, would like all CPU funtions done
the same way if we're going to do this though.

Thanks,
Nick

>
> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> 
> ---
>  target/ppc/excp_helper.c | 47 +++++++++++++++++++++-------------------
>  1 file changed, 25 insertions(+), 22 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 0712098cf7..704eddac63 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -1842,10 +1842,12 @@ static int p8_next_unmasked_interrupt(CPUPPCState *env)
>       PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | PPC_INTERRUPT_FIT |  \
>       PPC_INTERRUPT_PIT | PPC_INTERRUPT_THERM)
>  
> -static int p9_interrupt_powersave(CPUPPCState *env)
> +static int p9_interrupt_powersave(CPUPPCState *env,
> +                                  uint32_t pending_interrupts)
>  {
> +
>      /* External Exception */
> -    if ((env->pending_interrupts & PPC_INTERRUPT_EXT) &&
> +    if ((pending_interrupts & PPC_INTERRUPT_EXT) &&
>          (env->spr[SPR_LPCR] & LPCR_EEE)) {
>          bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
>          if (!heic || !FIELD_EX64_HV(env->msr) ||
> @@ -1854,48 +1856,49 @@ static int p9_interrupt_powersave(CPUPPCState *env)
>          }
>      }
>      /* Decrementer Exception */
> -    if ((env->pending_interrupts & PPC_INTERRUPT_DECR) &&
> +    if ((pending_interrupts & PPC_INTERRUPT_DECR) &&
>          (env->spr[SPR_LPCR] & LPCR_DEE)) {
>          return PPC_INTERRUPT_DECR;
>      }
>      /* Machine Check or Hypervisor Maintenance Exception */
>      if (env->spr[SPR_LPCR] & LPCR_OEE) {
> -        if (env->pending_interrupts & PPC_INTERRUPT_MCK) {
> +        if (pending_interrupts & PPC_INTERRUPT_MCK) {
>              return PPC_INTERRUPT_MCK;
>          }
> -        if (env->pending_interrupts & PPC_INTERRUPT_HMI) {
> +        if (pending_interrupts & PPC_INTERRUPT_HMI) {
>              return PPC_INTERRUPT_HMI;
>          }
>      }
>      /* Privileged Doorbell Exception */
> -    if ((env->pending_interrupts & PPC_INTERRUPT_DOORBELL) &&
> +    if ((pending_interrupts & PPC_INTERRUPT_DOORBELL) &&
>          (env->spr[SPR_LPCR] & LPCR_PDEE)) {
>          return PPC_INTERRUPT_DOORBELL;
>      }
>      /* Hypervisor Doorbell Exception */
> -    if ((env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) &&
> +    if ((pending_interrupts & PPC_INTERRUPT_HDOORBELL) &&
>          (env->spr[SPR_LPCR] & LPCR_HDEE)) {
>          return PPC_INTERRUPT_HDOORBELL;
>      }
>      /* Hypervisor virtualization exception */
> -    if ((env->pending_interrupts & PPC_INTERRUPT_HVIRT) &&
> +    if ((pending_interrupts & PPC_INTERRUPT_HVIRT) &&
>          (env->spr[SPR_LPCR] & LPCR_HVEE)) {
>          return PPC_INTERRUPT_HVIRT;
>      }
> -    if (env->pending_interrupts & PPC_INTERRUPT_RESET) {
> +    if (pending_interrupts & PPC_INTERRUPT_RESET) {
>          return PPC_INTERRUPT_RESET;
>      }
>      return 0;
>  }
>  
> -static int p9_next_unmasked_interrupt(CPUPPCState *env)
> +static int p9_next_unmasked_interrupt(CPUPPCState *env,
> +                                      uint32_t pending_interrupts)
>  {
>      CPUState *cs = env_cpu(env);
>  
>      /* Ignore MSR[EE] when coming out of some power management states */
>      bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;
>  
> -    assert((env->pending_interrupts & P9_UNUSED_INTERRUPTS) == 0);
> +    assert((pending_interrupts & P9_UNUSED_INTERRUPTS) == 0);
>  
>      if (cs->halted) {
>          if (env->spr[SPR_PSSCR] & PSSCR_EC) {
> @@ -1903,7 +1906,7 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
>               * When PSSCR[EC] is set, LPCR[PECE] controls which interrupts can
>               * wakeup the processor
>               */
> -            return p9_interrupt_powersave(env);
> +            return p9_interrupt_powersave(env, pending_interrupts);
>          } else {
>              /*
>               * When it's clear, any system-caused exception exits power-saving
> @@ -1914,12 +1917,12 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
>      }
>  
>      /* Machine check exception */
> -    if (env->pending_interrupts & PPC_INTERRUPT_MCK) {
> +    if (pending_interrupts & PPC_INTERRUPT_MCK) {
>          return PPC_INTERRUPT_MCK;
>      }
>  
>      /* Hypervisor decrementer exception */
> -    if (env->pending_interrupts & PPC_INTERRUPT_HDECR) {
> +    if (pending_interrupts & PPC_INTERRUPT_HDECR) {
>          /* LPCR will be clear when not supported so this will work */
>          bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
>          if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hdice) {
> @@ -1929,7 +1932,7 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
>      }
>  
>      /* Hypervisor virtualization interrupt */
> -    if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) {
> +    if (pending_interrupts & PPC_INTERRUPT_HVIRT) {
>          /* LPCR will be clear when not supported so this will work */
>          bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE);
>          if ((msr_ee || !FIELD_EX64_HV(env->msr)) && hvice) {
> @@ -1938,7 +1941,7 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
>      }
>  
>      /* External interrupt can ignore MSR:EE under some circumstances */
> -    if (env->pending_interrupts & PPC_INTERRUPT_EXT) {
> +    if (pending_interrupts & PPC_INTERRUPT_EXT) {
>          bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
>          bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
>          /* HEIC blocks delivery to the hypervisor */
> @@ -1950,20 +1953,20 @@ static int p9_next_unmasked_interrupt(CPUPPCState *env)
>      }
>      if (msr_ee != 0) {
>          /* Decrementer exception */
> -        if (env->pending_interrupts & PPC_INTERRUPT_DECR) {
> +        if (pending_interrupts & PPC_INTERRUPT_DECR) {
>              return PPC_INTERRUPT_DECR;
>          }
> -        if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) {
> +        if (pending_interrupts & PPC_INTERRUPT_DOORBELL) {
>              return PPC_INTERRUPT_DOORBELL;
>          }
> -        if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) {
> +        if (pending_interrupts & PPC_INTERRUPT_HDOORBELL) {
>              return PPC_INTERRUPT_HDOORBELL;
>          }
> -        if (env->pending_interrupts & PPC_INTERRUPT_PERFM) {
> +        if (pending_interrupts & PPC_INTERRUPT_PERFM) {
>              return PPC_INTERRUPT_PERFM;
>          }
>          /* EBB exception */
> -        if (env->pending_interrupts & PPC_INTERRUPT_EBB) {
> +        if (pending_interrupts & PPC_INTERRUPT_EBB) {
>              /*
>               * EBB exception must be taken in problem state and
>               * with BESCR_GE set.
> @@ -1989,7 +1992,7 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *env)
>          return p8_next_unmasked_interrupt(env);
>      case POWERPC_EXCP_POWER9:
>      case POWERPC_EXCP_POWER10:
> -        return p9_next_unmasked_interrupt(env);
> +        return p9_next_unmasked_interrupt(env, env->pending_interrupts);
>      default:
>          break;
>      }