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[14.200.18.130]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-218a1dcc748sm66166645ad.92.2024.12.17.17.44.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Dec 2024 17:44:57 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 18 Dec 2024 11:44:50 +1000 Message-Id: To: "Akihiko Odaki" , Cc: "Michael S. Tsirkin" , "Marcel Apfelbaum" , "Fabiano Rosas" , "Laurent Vivier" , "Paolo Bonzini" , "Dmitry Fleytman" , "Sriram Yagnaraman" Subject: Re: [PATCH 3/8] pci/msix: Implement PBA writes From: "Nicholas Piggin" X-Mailer: aerc 0.18.2 References: <20241212083502.1439033-1-npiggin@gmail.com> <20241212083502.1439033-4-npiggin@gmail.com> <5dd989ee-e9d3-4c49-9031-a4bc320bbaa9@daynix.com> In-Reply-To: <5dd989ee-e9d3-4c49-9031-a4bc320bbaa9@daynix.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri Dec 13, 2024 at 3:14 PM AEST, Akihiko Odaki wrote: > On 2024/12/12 17:34, Nicholas Piggin wrote: > > Implement MMIO PBA writes, 1 to trigger and 0 to clear. > >=20 > > This functionality is used by some qtests, which keep the msix irq > > masked and test irq pending via the PBA bits, for simplicity. Some > > tests expect to be able to clear the irq with a store, so a side-effect > > of this is that qpci_msix_pending() would actually clear the pending > > bit where it previously did not. This actually causes some [possibly > > buggy] tests to fail. So to avoid breakage until tests are re-examined, > > prior behavior of qpci_msix_pending() is kept by changing it to avoid > > clearing PBA. > >=20 > > A new function qpci_msix_test_clear_pending() is added for tests that > > do want the PBA clearing, and it will be used by XHCI and e1000e/igb > > tests in subsequent changes. > > The specification says software should never write Pending Bits and its= =20 > result is undefined. Tests should have an alternative method to clear=20 > Pending Bits. Thanks for correcting me. I guess qpci_msix_pending() should not be trying to write to the PBA either then. > A possible solution is to unmask the interrupt, wait until the Pending=20 > Bits get cleared, and mask it again. PCI spec says If a masked vector has its Pending bit set, and the associated underlying interrupt events are somehow satisfied (usually by software though the exact manner is function-specific), the function must clear the Pending bit, to avoid sending a spurious interrupt message later when software unmasks the vector. However, if a subsequent interrupt event occurs while the vector is still masked, the function must again set the Pending bit. It looks like e1000e acutally does that with e1000e_msix_clear{_one}. So perhaps this will work just with the e1000e ICR clearing patch. I will test. e1000e and igb are the only devices that call msix_clr_pending. Does that mean many others probably do not implement this behaviour correctly? Thanks, Nick