From: "Nicholas Piggin" <npiggin@gmail.com>
To: "Akihiko Odaki" <akihiko.odaki@daynix.com>, <qemu-devel@nongnu.org>
Cc: "Michael S . Tsirkin" <mst@redhat.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Dmitry Fleytman" <dmitry.fleytman@gmail.com>,
"Sriram Yagnaraman" <sriram.yagnaraman@ericsson.com>,
"Fabiano Rosas" <farosas@suse.de>,
"Laurent Vivier" <lvivier@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>
Subject: Re: [PATCH 4/5] qtest/e1000e|igb: Clear interrupt-cause bits after irq
Date: Sat, 21 Dec 2024 14:15:14 +1000 [thread overview]
Message-ID: <D6H35IACQM5F.2SKVF41KXO7GN@gmail.com> (raw)
In-Reply-To: <1b6ed10c-7dc7-4e27-9f84-d89c6c0adf55@daynix.com>
On Thu Dec 19, 2024 at 7:00 PM AEST, Akihiko Odaki wrote:
> On 2024/12/18 16:42, Nicholas Piggin wrote:
> > The e1000e and igb tests do not clear the ICR/EICR cause bits (or
> > set auto-clear) on seeing queue interrupts, which inhibits the
> > triggering of a new interrupt.
> >
> > Fix this by clearing the cause bits, and verify that the expected
> > cause bit was set.
> >
> > Cc: Michael S. Tsirkin <mst@redhat.com>
> > Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
> > Cc: Dmitry Fleytman <dmitry.fleytman@gmail.com>
> > Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
> > Cc: Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>
> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> > ---
> > tests/qtest/e1000e-test.c | 8 ++++++--
> > tests/qtest/igb-test.c | 8 ++++++--
> > 2 files changed, 12 insertions(+), 4 deletions(-)
> >
> > diff --git a/tests/qtest/e1000e-test.c b/tests/qtest/e1000e-test.c
> > index de9738fdb74..a69759da70e 100644
> > --- a/tests/qtest/e1000e-test.c
> > +++ b/tests/qtest/e1000e-test.c
> > @@ -64,8 +64,10 @@ static void e1000e_send_verify(QE1000E *d, int *test_sockets, QGuestAllocator *a
> > /* Put descriptor to the ring */
> > e1000e_tx_ring_push(d, &descr);
> >
> > - /* Wait for TX WB interrupt */
> > + /* Wait for TX WB interrupt (this clears the MSIX PBA) */
>
> It doesn't clear the MSI-X PBA unless the next patch is applied. This
> comment change should be moved to that patch.
Good catch. That was leftover from my improper PBA write patch.
> > e1000e_wait_isr(d, E1000E_TX0_MSG_ID);
> > + /* Read ICR which clears it ready for next interrupt, assert TXQ0 cause */
>
> I suggest the following to make this comment clearer:
> Read ICR to make it ready for next interrupt, assert TXQ0 cause
Sure.
Thanks,
Nick
next prev parent reply other threads:[~2024-12-21 4:15 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-18 7:42 [PATCH 0/5] qtest: pci and e1000e/igb msix fixes Nicholas Piggin
2024-12-18 7:42 ` [PATCH 1/5] qtest/pci: Enforce balanced iomap/unmap Nicholas Piggin
2024-12-19 9:03 ` Akihiko Odaki
2024-12-18 7:42 ` [PATCH 2/5] qtest/libqos/pci: Fix qpci_msix_enable sharing bar0 Nicholas Piggin
2024-12-18 7:42 ` [PATCH 3/5] qtest/libqos/pci: Do not write to PBA memory Nicholas Piggin
2024-12-18 7:42 ` [PATCH 4/5] qtest/e1000e|igb: Clear interrupt-cause bits after irq Nicholas Piggin
2024-12-19 9:00 ` Akihiko Odaki
2024-12-21 4:15 ` Nicholas Piggin [this message]
2024-12-18 7:42 ` [PATCH 5/5] qtest/e1000e|igb: Fix msix to re-trigger interrupts Nicholas Piggin
2024-12-19 8:53 ` Akihiko Odaki
2024-12-21 4:14 ` Nicholas Piggin
2024-12-21 4:26 ` Akihiko Odaki
2024-12-21 8:11 ` Nicholas Piggin
2024-12-21 9:26 ` Akihiko Odaki
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