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Mon, 13 Jan 2025 23:11:07 -0800 (PST) Received: from localhost ([1.146.73.114]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21a9f234977sm62463405ad.204.2025.01.13.23.11.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Jan 2025 23:11:07 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 14 Jan 2025 17:11:01 +1000 Message-Id: Cc: , "Daniel Henrique Barboza" , "Laurent Vivier" Subject: Re: [PATCH 3/9] ppc/ppc405: Remove CPU From: "Nicholas Piggin" To: "Richard Henderson" , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?C=C3=A9dric_Le_Goater?= , X-Mailer: aerc 0.18.2 References: <20250110141800.1587589-1-clg@redhat.com> <20250110141800.1587589-4-clg@redhat.com> <1c294e9e-8774-4e3c-874c-d64bcc0f7ce7@linaro.org> <08932dd4-f4d2-4eae-b237-2975c820cec1@linaro.org> In-Reply-To: <08932dd4-f4d2-4eae-b237-2975c820cec1@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sat Jan 11, 2025 at 2:25 AM AEST, Richard Henderson wrote: > On 1/10/25 08:15, Philippe Mathieu-Daud=C3=A9 wrote: > > Hi C=C3=A9dric, > >=20 > > Cc'ing Laurent & Richard for user emulation. > >=20 > ... > > The deprecation message (see previous patch) was about the > > "ppc ``ref405ep`` machine". Is that OK we remove these CPUs > > for user emulation? > >=20 > > $ qemu-ppc -cpu help|fgrep 405 > > PowerPC 405d2=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 PVR 20010000 > > PowerPC 405gpa=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 PVR 40110000 > > PowerPC 405gpb=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 PVR 40110040 > > PowerPC 405cra=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 PVR 40110041 > > PowerPC 405gpc=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 PVR 40110082 > > PowerPC 405gpd=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 PVR 401100c4 > > PowerPC 405gp=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 (alias for 405gpd) > > PowerPC 405crb=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 PVR 401100c5 > > PowerPC 405crc=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 PVR 40110145 > > PowerPC 405cr=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 (alias for 405crc) > > PowerPC 405gpe=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 (alias for 405crc) > > PowerPC npe405h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 P= VR 414100c0 > > PowerPC npe405h2=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 PVR 41= 410140 > > PowerPC 405ez=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 PVR 41511460 > > PowerPC npe405l=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 P= VR 416100c0 > > PowerPC 405d4=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 PVR 41810000 > > PowerPC 405=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 (alias for 405d4) > > PowerPC 405lp=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 PVR 41f10000 > > PowerPC 405gpr=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 PVR 50910951 > > PowerPC 405ep=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 PVR 51210950 > > Up to the ppc maintainers. I don't know of anything interesting at the u= ser-only level=20 > wrt these cpus. Just getting back to things after the break... We are looking at modeling some microcontrollers on the POWER chips. There is an OCC power management controller which is a 405 and some other weird cut down 405 derivatives, we're not up to those yet but we want to model them. We should be able to remove a bunch of boards and CPUs, I just haven't started looking, so might be easier to wait for a bit. If it's not causing others too much problem, could we leave this in for the time being? Thanks, Nick