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Sun, 04 May 2025 23:38:55 -0700 (PDT) Received: from localhost ([1.146.78.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22e151e9785sm47449495ad.65.2025.05.04.23.38.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 04 May 2025 23:38:55 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 05 May 2025 16:38:48 +1000 Message-Id: Cc: , "Dmitry Fleytman" , "Jason Wang" , "Sriram Yagnaraman" , "Fabiano Rosas" , "Laurent Vivier" , "Paolo Bonzini" Subject: Re: [PATCH v3 03/12] hw/net/e1000e|igb: Remove xitr_guest_value logic From: "Nicholas Piggin" To: "Akihiko Odaki" X-Mailer: aerc 0.19.0 References: <20250502031705.100768-1-npiggin@gmail.com> <20250502031705.100768-4-npiggin@gmail.com> <5576bcff-aa0a-44b7-a3e2-bc2389f9ffaf@daynix.com> In-Reply-To: <5576bcff-aa0a-44b7-a3e2-bc2389f9ffaf@daynix.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=npiggin@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon May 5, 2025 at 3:45 PM AEST, Akihiko Odaki wrote: > On 2025/05/02 12:16, Nicholas Piggin wrote: >> The guest value xITR logic is not required now that the write functions >> store necessary data to be read back, and internal users mask and shift >> fields they need as they go. >>=20 >> Signed-off-by: Nicholas Piggin >> --- >> hw/net/e1000e_core.c | 31 +++++++++++++++---------------- >> hw/net/igb_core.c | 16 +++++++++++++--- >> 2 files changed, 28 insertions(+), 19 deletions(-) >>=20 >> diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c >> index 96f74f1ea14..f8e6522f810 100644 >> --- a/hw/net/e1000e_core.c >> +++ b/hw/net/e1000e_core.c >> @@ -2563,18 +2563,6 @@ e1000e_mac_swsm_read(E1000ECore *core, int index) >> return val; >> } >> =20 >> -static uint32_t >> -e1000e_mac_itr_read(E1000ECore *core, int index) >> -{ >> - return core->itr_guest_value; >> -} >> - >> -static uint32_t >> -e1000e_mac_eitr_read(E1000ECore *core, int index) >> -{ >> - return core->eitr_guest_value[index - EITR]; >> -} >> - >> static uint32_t >> e1000e_mac_icr_read(E1000ECore *core, int index) >> { >> @@ -2792,7 +2780,6 @@ e1000e_set_itr(E1000ECore *core, int index, uint32= _t val) >> =20 >> trace_e1000e_irq_itr_set(val); >> =20 >> - core->itr_guest_value =3D interval; >> core->mac[index] =3D interval; >> } >> =20 >> @@ -2804,7 +2791,6 @@ e1000e_set_eitr(E1000ECore *core, int index, uint3= 2_t val) >> =20 >> trace_e1000e_irq_eitr_set(eitr_num, val); >> =20 >> - core->eitr_guest_value[eitr_num] =3D interval; >> core->mac[index] =3D interval; >> } >> =20 >> @@ -3029,6 +3015,7 @@ static const readops e1000e_macreg_readops[] =3D { >> e1000e_getreg(GSCN_1), >> e1000e_getreg(FCAL), >> e1000e_getreg(FLSWCNT), >> + e1000e_getreg(ITR), >> =20 >> [TOTH] =3D e1000e_mac_read_clr8, >> [GOTCH] =3D e1000e_mac_read_clr8, >> @@ -3062,7 +3049,6 @@ static const readops e1000e_macreg_readops[] =3D { >> [MPRC] =3D e1000e_mac_read_clr4, >> [BPTC] =3D e1000e_mac_read_clr4, >> [TSCTC] =3D e1000e_mac_read_clr4, >> - [ITR] =3D e1000e_mac_itr_read, >> [CTRL] =3D e1000e_get_ctrl, >> [TARC1] =3D e1000e_get_tarc, >> [SWSM] =3D e1000e_mac_swsm_read, >> @@ -3087,7 +3073,7 @@ static const readops e1000e_macreg_readops[] =3D { >> [RETA ... RETA + 31] =3D e1000e_mac_readreg, >> [RSSRK ... RSSRK + 31] =3D e1000e_mac_readreg, >> [MAVTV0 ... MAVTV3] =3D e1000e_mac_readreg, >> - [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] =3D e1000e_mac_eitr_read >> + [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] =3D e1000e_mac_readreg, >> }; >> enum { E1000E_NREADOPS =3D ARRAY_SIZE(e1000e_macreg_readops) }; >> =20 >> @@ -3517,13 +3503,26 @@ void e1000e_core_pre_save(E1000ECore *core) >> core->tx[i].skip_cp =3D true; >> } >> } >> + >> + /* back compat, QEMU moves xITR in itr_guest_value state */ >> + core->itr_guest_value =3D core->mac[ITR]; >> + for (i =3D 0; i < E1000E_MSIX_VEC_NUM; i++) { >> + core->eitr_guest_value[i] =3D core->mac[EITR + i]; >> + } >> } >> =20 >> int >> e1000e_core_post_load(E1000ECore *core) >> { >> + int i; >> NetClientState *nc =3D qemu_get_queue(core->owner_nic); >> =20 >> + /* back compat */ >> + core->mac[ITR] =3D core->itr_guest_value; >> + for (i =3D 0; i < E1000E_MSIX_VEC_NUM; i++) { >> + core->mac[EITR + i] =3D core->eitr_guest_value[i]; >> + } >> + >> /* >> * nc.link_down can't be migrated, so infer link_down according >> * to link status bit in core.mac[STATUS]. >> diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c >> index 39e3ce1c8fe..271c54380e9 100644 >> --- a/hw/net/igb_core.c >> +++ b/hw/net/igb_core.c >> @@ -2880,7 +2880,7 @@ igb_mac_swsm_read(IGBCore *core, int index) >> static uint32_t >> igb_mac_eitr_read(IGBCore *core, int index) >> { >> - return core->eitr_guest_value[index - EITR0]; >> + return core->mac[index - EITR0]; >> } >> =20 >> static uint32_t igb_mac_vfmailbox_read(IGBCore *core, int index) >> @@ -3046,8 +3046,7 @@ igb_set_eitr(IGBCore *core, int index, uint32_t va= l) >> =20 >> trace_igb_irq_eitr_set(eitr_num, val); >> =20 >> - core->eitr_guest_value[eitr_num] =3D val & ~E1000_EITR_CNT_IGNR; >> - core->mac[index] =3D val & 0x7FFE; >> + core->mac[index] =3D val; > > This change will keep the CNT_INGR although the specification says it=20 > "is always read as zero". I will fix. Thanks, Nick