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Sun, 04 May 2025 23:50:04 -0700 (PDT) Received: from localhost ([1.146.78.151]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74058d7ada5sm6023976b3a.20.2025.05.04.23.49.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 04 May 2025 23:50:03 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 05 May 2025 16:49:57 +1000 Message-Id: Cc: , "Dmitry Fleytman" , "Jason Wang" , "Sriram Yagnaraman" , "Fabiano Rosas" , "Laurent Vivier" , "Paolo Bonzini" Subject: Re: [PATCH v3 11/12] net/e1000e|igb: Fix interrupt throttling rearming From: "Nicholas Piggin" To: "Akihiko Odaki" X-Mailer: aerc 0.19.0 References: <20250502031705.100768-1-npiggin@gmail.com> <20250502031705.100768-12-npiggin@gmail.com> <57c9b65a-bfdf-47e6-a438-6559f791f7dd@daynix.com> In-Reply-To: <57c9b65a-bfdf-47e6-a438-6559f791f7dd@daynix.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=npiggin@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon May 5, 2025 at 4:03 PM AEST, Akihiko Odaki wrote: > On 2025/05/02 12:17, Nicholas Piggin wrote: >> Timer expiry that results in an interrupt does not rearm the timer so >> an interrupt can appear immediately after the interrupt generated by >> timer expiry. >>=20 >> Fix this by rearming the throttle timer when a delayed interrupt is >> processed. e1000e gets this by reusing the e1000e_msix_notify() >> logic, igb calls igb_intrmgr_rearm_timer() directly. >>=20 >> Signed-off-by: Nicholas Piggin >> --- >> hw/net/e1000e_core.c | 5 ++-- >> hw/net/igb_core.c | 55 ++++++++++++++++++++++++++------------------ >> 2 files changed, 35 insertions(+), 25 deletions(-) >>=20 >> diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c >> index d53f70065ef..2932122c04b 100644 >> --- a/hw/net/e1000e_core.c >> +++ b/hw/net/e1000e_core.c >> @@ -218,7 +218,7 @@ static uint32_t find_msix_causes(E1000ECore *core, i= nt vec) >> } >> =20 >> static void >> -e1000e_msix_auto_clear_mask(E1000ECore *core, uint32_t cause); >> +e1000e_msix_notify(E1000ECore *core, uint32_t causes); >> =20 >> static void >> e1000e_intrmgr_on_msix_throttling_timer(void *opaque) >> @@ -233,8 +233,7 @@ e1000e_intrmgr_on_msix_throttling_timer(void *opaque= ) >> causes =3D find_msix_causes(core, idx) & core->mac[IMS] & core->ma= c[ICR]; >> if (causes) { >> trace_e1000e_irq_msix_notify_postponed_vec(idx); >> - msix_notify(core->owner, causes); >> - e1000e_msix_auto_clear_mask(core, causes); >> + e1000e_msix_notify(core, causes); >> } >> } >> =20 >> diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c >> index 035637f81f8..cc25a1d5baa 100644 >> --- a/hw/net/igb_core.c >> +++ b/hw/net/igb_core.c >> @@ -152,11 +152,14 @@ igb_intrmgr_arm_timer(IGBIntrDelayTimer *timer, in= t64_t delay_ns) >> static inline void >> igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer) >> { >> - uint32_t interval =3D (timer->core->mac[timer->delay_reg] & >> - E1000_EITR_INTERVAL) >> 2; >> - int64_t delay_ns =3D (int64_t)interval * timer->delay_resolution_ns= ; >> + uint32_t eitr =3D timer->core->mac[timer->delay_reg]; >> =20 >> - igb_intrmgr_arm_timer(timer, delay_ns); >> + if (eitr !=3D 0) { >> + uint32_t interval =3D (eitr & E1000_EITR_INTERVAL) >> 2; >> + int64_t delay_ns =3D (int64_t)interval * timer->delay_resolutio= n_ns; >> + >> + igb_intrmgr_arm_timer(timer, delay_ns); >> + } >> } >> =20 >> static void >> @@ -168,21 +171,7 @@ igb_intmgr_timer_resume(IGBIntrDelayTimer *timer) >> } >> =20 >> static void >> -igb_intrmgr_on_msix_throttling_timer(void *opaque) >> -{ >> - IGBIntrDelayTimer *timer =3D opaque; >> - IGBCore *core =3D timer->core; >> - int vector =3D timer - &core->eitr[0]; >> - uint32_t causes; >> - >> - timer->running =3D false; >> - >> - causes =3D core->mac[EICR] & core->mac[EIMS]; >> - if (causes & BIT(vector)) { >> - trace_e1000e_irq_msix_notify_postponed_vec(vector); >> - igb_msix_notify(core, vector); >> - } >> -} >> +igb_intrmgr_on_msix_throttling_timer(void *opaque); >> =20 >> static void >> igb_intrmgr_initialize_all_timers(IGBCore *core, bool create) >> @@ -2258,9 +2247,7 @@ igb_postpone_interrupt(IGBIntrDelayTimer *timer) >> return true; >> } >> =20 >> - if (timer->core->mac[timer->delay_reg] !=3D 0) { >> - igb_intrmgr_rearm_timer(timer); >> - } >> + igb_intrmgr_rearm_timer(timer); >> =20 >> return false; >> } >> @@ -2284,6 +2271,30 @@ static void igb_send_msix(IGBCore *core, uint32_t= causes) >> } >> } >> =20 >> +static void >> +igb_intrmgr_on_msix_throttling_timer(void *opaque) >> +{ >> + IGBIntrDelayTimer *timer =3D opaque; >> + IGBCore *core =3D timer->core; >> + int vector =3D timer - &core->eitr[0]; >> + uint32_t causes; >> + >> + timer->running =3D false; >> + >> + causes =3D core->mac[EICR] & core->mac[EIMS]; >> + if (causes & BIT(vector)) { >> + /* >> + * The moderation counter is loaded with interval value wheneve= r the >> + * interrupt is signaled. This includes when the interrupt is s= ignaled >> + * by the counter reaching 0. >> + */ >> + igb_intrmgr_rearm_timer(timer); >> + >> + trace_e1000e_irq_msix_notify_postponed_vec(vector); >> + igb_msix_notify(core, vector); >> + } >> +} >> + > > I wonder why the definition is moved. This patch adds a=20 > igb_intrmgr_rearm_timer() call but it's already placed earlier than this= =20 > function. Hmm, I did require moving it at one point, but I must have reworked it enough to avoid it. That makes the patch smaller and nicer. Another good catch. Thanks, Nick