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Thu, 08 May 2025 06:31:08 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200:a451:a252:64ea:9a0e]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442cd32f238sm37108665e9.11.2025.05.08.06.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 06:31:08 -0700 (PDT) Mime-Version: 1.0 Date: Thu, 08 May 2025 15:31:07 +0200 Message-Id: Subject: Re: [PATCH 1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit Cc: , , , , "linux-riscv" To: "Atish Patra" , "Anup Patel" , "Atish Patra" , "Paul Walmsley" , "Palmer Dabbelt" , "Alexandre Ghiti" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20250505-kvm_lazy_enable_stateen-v1-0-3bfc4008373c@rivosinc.com> <20250505-kvm_lazy_enable_stateen-v1-1-3bfc4008373c@rivosinc.com> In-Reply-To: <20250505-kvm_lazy_enable_stateen-v1-1-3bfc4008373c@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250508_063110_250032_C2BE17EA X-CRM114-Status: UNSURE ( 6.33 ) X-CRM114-Notice: Please train this message. X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+kvm-riscv=archiver.kernel.org@lists.infradead.org 2025-05-05T14:39:26-07:00, Atish Patra : > Currently, we enable the smstateen bit at vcpu configure time by > only checking the presence of required ISA extensions. > > These bits are not required to be enabled if the guest never uses > the corresponding architectural state. Enable the smstaeen bits > at runtime lazily upon first access. What is the advantage of enabling them lazily? To make the trap useful, we would have to lazily perform initialization of the AIA. I think it would require notable changes to AIA, though... Thanks. -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EB5B4B1E6D for ; Thu, 8 May 2025 13:31:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746711072; cv=none; b=L4qK7f29Ivv9ROso+x4a6sIyveWyFi2OnDEhpIsDWIdST1dP2P/xeM5IDCntS45EikK02MeBTqLbEtmGC1YRuPBVcmDUWt0W/pW/g7SwbbwYuK9sabWhLadiDai9eTnP15p+KGfif7sQvrfUVQOO8nH2sptoq5HYGIq6R+1fuPo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746711072; c=relaxed/simple; bh=PTIxFNCKUc6RCmBCpLXRdipjalC9UH6iNZPNrIkp7Uw=; h=Mime-Version:Content-Type:Date:Message-Id:Subject:Cc:To:From: References:In-Reply-To; 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Thu, 08 May 2025 06:31:08 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200:a451:a252:64ea:9a0e]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442cd32f238sm37108665e9.11.2025.05.08.06.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 06:31:08 -0700 (PDT) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 08 May 2025 15:31:07 +0200 Message-Id: Subject: Re: [PATCH 1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit Cc: , , , , "linux-riscv" To: "Atish Patra" , "Anup Patel" , "Atish Patra" , "Paul Walmsley" , "Palmer Dabbelt" , "Alexandre Ghiti" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20250505-kvm_lazy_enable_stateen-v1-0-3bfc4008373c@rivosinc.com> <20250505-kvm_lazy_enable_stateen-v1-1-3bfc4008373c@rivosinc.com> In-Reply-To: <20250505-kvm_lazy_enable_stateen-v1-1-3bfc4008373c@rivosinc.com> 2025-05-05T14:39:26-07:00, Atish Patra : > Currently, we enable the smstateen bit at vcpu configure time by > only checking the presence of required ISA extensions. > > These bits are not required to be enabled if the guest never uses > the corresponding architectural state. Enable the smstaeen bits > at runtime lazily upon first access. What is the advantage of enabling them lazily? To make the trap useful, we would have to lazily perform initialization of the AIA. I think it would require notable changes to AIA, though... Thanks. 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Thu, 08 May 2025 06:31:08 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200:a451:a252:64ea:9a0e]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-442cd32f238sm37108665e9.11.2025.05.08.06.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 May 2025 06:31:08 -0700 (PDT) Mime-Version: 1.0 Date: Thu, 08 May 2025 15:31:07 +0200 Message-Id: Subject: Re: [PATCH 1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit Cc: , , , , "linux-riscv" To: "Atish Patra" , "Anup Patel" , "Atish Patra" , "Paul Walmsley" , "Palmer Dabbelt" , "Alexandre Ghiti" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20250505-kvm_lazy_enable_stateen-v1-0-3bfc4008373c@rivosinc.com> <20250505-kvm_lazy_enable_stateen-v1-1-3bfc4008373c@rivosinc.com> In-Reply-To: <20250505-kvm_lazy_enable_stateen-v1-1-3bfc4008373c@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250508_063110_239146_6E0E118E X-CRM114-Status: UNSURE ( 6.33 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org 2025-05-05T14:39:26-07:00, Atish Patra : > Currently, we enable the smstateen bit at vcpu configure time by > only checking the presence of required ISA extensions. > > These bits are not required to be enabled if the guest never uses > the corresponding architectural state. Enable the smstaeen bits > at runtime lazily upon first access. What is the advantage of enabling them lazily? To make the trap useful, we would have to lazily perform initialization of the AIA. I think it would require notable changes to AIA, though... Thanks. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv