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Tue, 24 Jun 2025 06:48:30 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200:b00d:6d5f:6e67:f5e8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-453646d14f3sm142211175e9.13.2025.06.24.06.48.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jun 2025 06:48:29 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 24 Jun 2025 15:48:29 +0200 Message-Id: Cc: , "Alistair Francis" , "Weiwei Li" , "Liu Zhiwei" , "Atish Patra" , To: "Daniel Henrique Barboza" , From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= Subject: Re: [PATCH 1/2] target/riscv: disable *stimecmp interrupts without *envcfg.STCE References: <20250623165329.2759651-1-rkrcmar@ventanamicro.com> <20250623165329.2759651-2-rkrcmar@ventanamicro.com> <0811914e-623e-41a2-a54b-8ce42f45740c@ventanamicro.com> In-Reply-To: <0811914e-623e-41a2-a54b-8ce42f45740c@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=rkrcmar@ventanamicro.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org 2025-06-23T18:39:02-03:00, Daniel Henrique Barboza : > Hi Radim, > > It seems like this patch is breaking 'make check-functional': That is a nice command to know of, thanks! > 12/12 qemu:func-quick+func-riscv64 / func-riscv64-riscv_opensbi TIMEOUT= 90.06s killed by signal 15 SIGTERM > > Checking the logs I verified that the problem can be reproduced by runnin= g the > 'spike' machine as follows: > > $ ./build/qemu-system-riscv64 -M spike --nographic > Segmentation fault (core dumped) > > The expected result is to boot opensbi. The problem can't be reproduced w= ith > the 'virt' board, so something that you did here impacted 'spike' in part= icular > for some reason. Uff, mtimer is NULL on spike: 0x0000555555c46618 in riscv_timer_write_timecmp (env=3Denv@entry=3D0x5555= 56888270, timer=3D0x5555568a61e0, timecmp=3D0, delta=3Ddelta@entry=3D0, tim= er_irq=3Dtimer_irq@entry=3D32) at ../target/riscv/time_helper.c:49 49 uint32_t timebase_freq =3D mtimer->timebase_freq; (gdb) bt #0 0x0000555555c46618 in riscv_timer_write_timecmp (env=3Denv@entry=3D0x= 555556888270, timer=3D0x5555568a61e0, timecmp=3D0, delta=3Ddelta@entry=3D0,= timer_irq=3Dtimer_irq@entry=3D32) at ../target/riscv/time_helper.c:49 #1 0x0000555555c6eb9e in write_menvcfg (env=3D0x555556888270, csrno=3D, val=3D, ra=3D140736012591329) at ../target/ri= scv/csr.c:3214 #2 0x0000555555c6a181 in riscv_csrrw_do64 (env=3Denv@entry=3D0x555556888= 270, csrno=3D, ret_value=3Dret_value@entry=3D0x0, new_value= =3D, write_mask=3D, ra=3D140736012591329) at = ../target/riscv/csr.c:5579 [...] (gdb) p mtimer $1 =3D (RISCVAclintMTimerState *) 0x0 (gdb) p timer $2 =3D (QEMUTimer *) 0x5555568a61e0 (gdb) p *timer $3 =3D {expire_time =3D -1, timer_list =3D 0x55555666b840, cb =3D 0x55555= 5c465d0 , opaque =3D 0x5555568856b0, next =3D 0x0, attribu= tes =3D 0, scale =3D 1} I'll try to figure out is going on, but `make check-functional` passes with this hack: diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index 81a6a6394502..a2092206cb20 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -44,10 +44,8 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUT= imer *timer, uint64_t timecmp, uint64_t delta, uint32_t timer_irq) { - uint64_t diff, ns_diff, next; + uint64_t diff, ns_diff, next, timebase_freq, rtc_r; RISCVAclintMTimerState *mtimer =3D env->rdtime_fn_arg; - uint32_t timebase_freq =3D mtimer->timebase_freq; - uint64_t rtc_r =3D env->rdtime_fn(env->rdtime_fn_arg) + delta; =20 /* * *envcfg.STCE disables *stimecmp interrupts, but still allows higher @@ -59,6 +57,13 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUT= imer *timer, return; } =20 + if (!mtimer) { + return; + } + + timebase_freq =3D mtimer->timebase_freq; + rtc_r =3D env->rdtime_fn(env->rdtime_fn_arg) + delta; + if (timecmp <=3D rtc_r) { /* * If we're setting an stimecmp value in the "past",