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Tue, 08 Jul 2025 04:10:18 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kbuild@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 08 Jul 2025 13:10:17 +0200 Message-Id: Subject: Re: [External] [PATCH] RISC-V: store percpu offset in CSR_SCRATCH Cc: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , "linux-riscv" , To: "yunhui cui" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20250704084500.62688-1-cuiyunhui@bytedance.com> In-Reply-To: 2025-07-08T18:07:27+08:00, yunhui cui : > This patch cleverly differentiates whether an exception originates > from user mode or kernel mode. However, there's still an issue with > using CSR_SCRATCH: each time handle_exception() is called, the > following instructions must be executed: > > REG_L s0, TASK_TI_CPU(tp) > slli s0, s0, 3 > la s1, __per_cpu_offset > add s1, s1, s0 > REG_L s1, 0(s1) > csrw CSR_SCRATCH, s1 We can minimize the cost at exception entry by storing the precomputed offset in thread_info, which bloats the struct, and also incurs update cost on cpu migration, but should still be a net performance gain. The minimal code at exception entry would be: REG_L s0, TASK_TI_PERCPU_OFFSET(tp) csrw CSR_SCRATCH, s0 > Should we consider adding a dedicated CSR (e.g., CSR_SCRATCH2) to > store the percpu offset instead? > See: https://lists.riscv.org/g/tech-privileged/topic/113437553#msg2506 It would be nice to gather more data on the CSR_SCRATCH approach. Basically, the overhead of "REG_L s0, TASK_TI_PERCPU_OFFSET(tp)". (Or the longer sequence if we think it is worth it.) Can you benchmark the patch after reverting percpu.h, so we include the overhead of switching CSR_SCRATCH, but without any benefits provided by the per-cpu offset? The baseline would be the patch with reverted percpu.h, and reverted the sequence that sets the CSR_SCRATCH in handle_exception, so we roughly estimate the benefit of adding CSR_SCRATCH2. The CSR_SCRATCH2 does add overhead to hardware, and to domain context switches, and we also have to do something else for a few years anyway, because it's not even ratified... It's possible we might not benefit enough from CSR_SCRATCH2 to make a good case for it. Thanks. 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Tue, 08 Jul 2025 04:10:18 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200:f873:aafc:f154:af28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b4708d0beesm12854474f8f.36.2025.07.08.04.10.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jul 2025 04:10:18 -0700 (PDT) Mime-Version: 1.0 Date: Tue, 08 Jul 2025 13:10:17 +0200 Message-Id: Subject: Re: [External] [PATCH] RISC-V: store percpu offset in CSR_SCRATCH Cc: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , "linux-riscv" , To: "yunhui cui" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20250704084500.62688-1-cuiyunhui@bytedance.com> In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250708_041020_281970_6C2C3BC9 X-CRM114-Status: GOOD ( 11.91 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org 2025-07-08T18:07:27+08:00, yunhui cui : > This patch cleverly differentiates whether an exception originates > from user mode or kernel mode. However, there's still an issue with > using CSR_SCRATCH: each time handle_exception() is called, the > following instructions must be executed: > > REG_L s0, TASK_TI_CPU(tp) > slli s0, s0, 3 > la s1, __per_cpu_offset > add s1, s1, s0 > REG_L s1, 0(s1) > csrw CSR_SCRATCH, s1 We can minimize the cost at exception entry by storing the precomputed offset in thread_info, which bloats the struct, and also incurs update cost on cpu migration, but should still be a net performance gain. The minimal code at exception entry would be: REG_L s0, TASK_TI_PERCPU_OFFSET(tp) csrw CSR_SCRATCH, s0 > Should we consider adding a dedicated CSR (e.g., CSR_SCRATCH2) to > store the percpu offset instead? > See: https://lists.riscv.org/g/tech-privileged/topic/113437553#msg2506 It would be nice to gather more data on the CSR_SCRATCH approach. Basically, the overhead of "REG_L s0, TASK_TI_PERCPU_OFFSET(tp)". (Or the longer sequence if we think it is worth it.) Can you benchmark the patch after reverting percpu.h, so we include the overhead of switching CSR_SCRATCH, but without any benefits provided by the per-cpu offset? The baseline would be the patch with reverted percpu.h, and reverted the sequence that sets the CSR_SCRATCH in handle_exception, so we roughly estimate the benefit of adding CSR_SCRATCH2. The CSR_SCRATCH2 does add overhead to hardware, and to domain context switches, and we also have to do something else for a few years anyway, because it's not even ratified... It's possible we might not benefit enough from CSR_SCRATCH2 to make a good case for it. Thanks. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv