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From: Alejandro Vallejo <alejandro.garciavallejo@amd.com>
To: Stefano Stabellini <stefano.stabellini@amd.com>,
	<xen-devel@lists.xenproject.org>
Cc: <jbeulich@suse.com>, <andrew.cooper3@citrix.com>,
	<roger.pau@citrix.com>, <Xenia.Ragiadakou@amd.com>,
	<Jason.Andryuk@amd.com>
Subject: Re: [PATCH v2 2/2] xen/x86: introduce MCE_NONFATAL
Date: Wed, 9 Jul 2025 11:46:58 +0200	[thread overview]
Message-ID: <DB7FGG6STQMD.3FT6NRT4CI13@amd.com> (raw)
In-Reply-To: <20250708183238.3104638-2-stefano.stabellini@amd.com>

On Tue Jul 8, 2025 at 8:32 PM CEST, Stefano Stabellini wrote:
> Today, checking for non-fatal MCE errors on AMD is very invasive: it
> involves a periodic timer interrupting the physical CPU execution at
> regular intervals. Moreover, when the timer fires, the handler sends an
> IPI to all physical CPUs.
>
> Both these actions are disruptive in terms of latency and deterministic
> execution times for real-time workloads. They might miss a deadline due
> to one of these IPIs. Make it possible to disable non-fatal MCE errors
> checking with a new Kconfig option (MCE_NONFATAL).
>
> Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>

LGTM.

    Reviewed-by: Alejandro Vallejo <alejandro.garciavallejo@amd.com>

Cheers,
Alejandro


  reply	other threads:[~2025-07-09  9:47 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-08 18:32 [PATCH v2 0/2] Xen real-time x86 Stefano Stabellini
2025-07-08 18:32 ` [PATCH v2 1/2] xen/x86: don't send IPI to sync TSC when it is reliable Stefano Stabellini
2025-07-09  9:44   ` Alejandro Vallejo
2025-07-10  6:53   ` Jan Beulich
2025-07-11  1:34     ` Stefano Stabellini
2025-07-11  6:10       ` Jan Beulich
2025-07-08 18:32 ` [PATCH v2 2/2] xen/x86: introduce MCE_NONFATAL Stefano Stabellini
2025-07-09  9:46   ` Alejandro Vallejo [this message]
2025-07-09 15:00     ` Jan Beulich

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