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[89.103.73.235]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b472259842sm16047493f8f.72.2025.07.09.07.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jul 2025 07:20:39 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kbuild@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 09 Jul 2025 16:20:38 +0200 Message-Id: Subject: Re: [External] [PATCH] RISC-V: store percpu offset in CSR_SCRATCH Cc: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , "linux-riscv" , To: "yunhui cui" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20250704084500.62688-1-cuiyunhui@bytedance.com> In-Reply-To: 2025-07-09T19:42:26+08:00, yunhui cui : > Bench platform: Spacemit(R) X60 > No changes: > 6.77, 6.791, 6.792, 6.826, 6.784, 6.839, 6.776, 6.733, 6.795, 6.763 > Geometric mean: 6.786839305 > Reusing the current scratch: > 7.085, 7.09, 7.021, 7.089, 7.068, 7.034, 7.06, 7.062, 7.065, 7.051 > Geometric mean: 7.062466876 Great results. > A degradation of approximately 4.06% is observed. The possible cause > of the degradation is that the CSR_TVEC register is set every time a > kernel/user exception occurs. I assume the same. > The following is the patch without percpu optimization, which only > tests the overhead of separating exceptions into kernel and user > modes. Is the overhead above with this patch? And when we then use the CSR_SCRATCH for percpu, does it degrade even further? Thanks. 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[89.103.73.235]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b472259842sm16047493f8f.72.2025.07.09.07.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jul 2025 07:20:39 -0700 (PDT) Mime-Version: 1.0 Date: Wed, 09 Jul 2025 16:20:38 +0200 Message-Id: Subject: Re: [External] [PATCH] RISC-V: store percpu offset in CSR_SCRATCH Cc: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , "linux-riscv" , To: "yunhui cui" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20250704084500.62688-1-cuiyunhui@bytedance.com> In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250709_072041_922721_9E9C6CF1 X-CRM114-Status: UNSURE ( 8.35 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org 2025-07-09T19:42:26+08:00, yunhui cui : > Bench platform: Spacemit(R) X60 > No changes: > 6.77, 6.791, 6.792, 6.826, 6.784, 6.839, 6.776, 6.733, 6.795, 6.763 > Geometric mean: 6.786839305 > Reusing the current scratch: > 7.085, 7.09, 7.021, 7.089, 7.068, 7.034, 7.06, 7.062, 7.065, 7.051 > Geometric mean: 7.062466876 Great results. > A degradation of approximately 4.06% is observed. The possible cause > of the degradation is that the CSR_TVEC register is set every time a > kernel/user exception occurs. I assume the same. > The following is the patch without percpu optimization, which only > tests the overhead of separating exceptions into kernel and user > modes. Is the overhead above with this patch? And when we then use the CSR_SCRATCH for percpu, does it degrade even further? Thanks. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv