From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30506264618; Wed, 16 Jul 2025 20:06:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752696419; cv=none; b=d5zhnPGhqJ6/oT4oZIuIyyYrAzjYrDerihr73diZ1jROkGHNm9/qJQr5Rdvnby+Nyx6EtNVa2tK0Z8YTGzgFSUuuTglq0eIZv7OPRTsikWERQlHf68rH5SNU4F9XJm/w1kvOz3wmiMrSdnOZcz4scwuU5INrdbAQPet+mPDJ3ow= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752696419; c=relaxed/simple; bh=XnBmWX7GkRUoTQVZ0sClSDh7tgJspj9XYLtujPHUBSc=; h=Mime-Version:Content-Type:Date:Message-Id:Subject:Cc:To:From: References:In-Reply-To; b=IJG5ijP0YtZK0KwlEywHJDOsNURUFBjIxihMlY1KMtG39NHsZRGYj+IxF+uiLgqlgi4r63GX3kiXaKOZ9p2Qrxfg9+gzifZuXI5sJQJEBicLDJVN8KYQbeHMj/sOtNqsHPzev8kIhSPB3+SEygksxeEA8rKLrnMLvYvCWrBV/UQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NKtFW5m7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NKtFW5m7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06D58C4CEE7; Wed, 16 Jul 2025 20:06:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752696418; bh=XnBmWX7GkRUoTQVZ0sClSDh7tgJspj9XYLtujPHUBSc=; h=Date:Subject:Cc:To:From:References:In-Reply-To:From; b=NKtFW5m7K/CZk7pEqB0Z3ndUHmRqKddy+2pjJ0l9X7yNLmzlSi4Utmrgz9I1eBGZn 5mMOOeFRJVq8YKROOH5jiTP6ilsMP7ZWvgCMCNoFCrWS/XPIoEfn/2TLexm71K+5Bx o+Q8bMUCcowujM/JlWBARli7ooDVGmWcWQixz4ppHEuKqJCgBapYukt7TSO5tJlcZR kqopylNtdsujZj9CfYj3eI07Dg4cE6Rmz6aZBBnLvFmrrygREePO5Ybu6XseQIH81k WmRqRSaE8/zrvCM0xmX6cndxkvMnY5cCG0TiZFolDKtZpAfgvtdflvaoIrjT8jcVrf Kse27JsTG/0hQ== Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 16 Jul 2025 22:06:54 +0200 Message-Id: Subject: Re: [PATCH v9] rust: kernel: add support for bits/genmask macros Cc: "Miguel Ojeda" , "Alex Gaynor" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , , , "Alexandre Courbot" To: "Daniel Almeida" From: "Danilo Krummrich" References: <20250714-topics-tyr-genmask2-v9-1-9e6422cbadb6@collabora.com> <705CD461-60D9-492E-B82F-C88A848A4348@collabora.com> <1DCA3EA2-5CBB-4193-B1D3-7E286C344A14@collabora.com> In-Reply-To: On Wed Jul 16, 2025 at 9:49 PM CEST, Danilo Krummrich wrote: > On Wed Jul 16, 2025 at 9:44 PM CEST, Daniel Almeida wrote: >> I guess this is the same problem as u64: drivers will usually have eithe= r >> i32s/u32s and this would require a cast. > > I don't understand this argument? We usualy use usize for such things, no= ? I already thought in terms of the register!() macro, which deals with targe= t types for us anyways. Without that, you're right, u32 is better.