From: "Michael Walle" <mwalle@kernel.org>
To: "Stephan Gerhold" <stephan.gerhold@linaro.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
"Danilo Krummrich" <dakr@kernel.org>,
"Stephen Boyd" <sboyd@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Dmitry Baryshkov" <lumag@kernel.org>
Cc: "Rob Clark" <robin.clark@oss.qualcomm.com>,
"Abhinav Kumar" <abhinav.kumar@linux.dev>,
"Jessica Zhang" <jessica.zhang@oss.qualcomm.com>,
"Sean Paul" <sean@poorly.run>,
"Marijn Suijten" <marijn.suijten@somainline.org>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Rob Herring" <robh@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>,
<freedreno@lists.freedesktop.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>,
"Abel Vesa" <abel.vesa@linaro.org>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konradybcio@kernel.org>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Nishanth Menon" <nm@ti.com>
Subject: Re: [PATCH 0/2] driver core: platform: / drm/msm: dp: Delay applying clock defaults
Date: Mon, 18 Aug 2025 14:47:55 +0200 [thread overview]
Message-ID: <DC5KCSEUZQUJ.3KPENNUQBUFM8@kernel.org> (raw)
In-Reply-To: <20250814-platform-delay-clk-defaults-v1-0-4aae5b33512f@linaro.org>
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Hi,
On Thu Aug 14, 2025 at 11:18 AM CEST, Stephan Gerhold wrote:
> Michael had a somewhat related problem in the PVR driver recently [1],
> where of_clk_set_defaults() needs to be called a second time from the PVR
> driver (after the GPU has been powered on) to make the assigned-clock-rates
> work correctly.
I've come back to this and just noticed that the
assigned-clock-rates do actually work. What doesn't work is the
caching of the clock rate. That bug was then masked by calling
of_clk_set_defaults() again in the driver.
Here is what the driver is doing:
(1) driver gets handle to the clock with clk_get().
(2) driver enables clock with clk_enable()
(3) driver does a clk_get_rate() which returns 0, although there is
already a hardware default in my case. That got me curious
again..
Now on the k3 platforms the clocking is handled by a firmware and it
appears that the firmware is reporting a clock rate of 0 unless the
clock is actually enabled. After the clock is enabled it will report
the correct rate. (FWIW, I can modify the hardware/firmware default
rate with the assigned-clock-rates DT property).
I've hacked the clock driver to register all clocks with
CLK_GET_RATE_NO_CACHE and then everything is working as expected.
I'm no expert for the clocking framework, but it seems that
clk_get() will ask the HW for the clk rate and caches it early on.
-michael
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prev parent reply other threads:[~2025-08-18 12:48 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-14 9:18 [PATCH 0/2] driver core: platform: / drm/msm: dp: Delay applying clock defaults Stephan Gerhold
2025-08-14 9:18 ` [PATCH 1/2] driver core: platform: Add option to skip/delay " Stephan Gerhold
2025-08-14 9:18 ` [PATCH 2/2] drm/msm: dp: Delay applying clock defaults until PHY is fully enabled Stephan Gerhold
2025-08-14 11:55 ` [PATCH 0/2] driver core: platform: / drm/msm: dp: Delay applying clock defaults Dmitry Baryshkov
2025-08-14 12:38 ` Stephan Gerhold
2025-08-16 13:55 ` Dmitry Baryshkov
2025-08-18 9:41 ` Stephan Gerhold
2025-08-19 1:19 ` Dmitry Baryshkov
2025-08-19 10:41 ` Stephan Gerhold
2025-08-19 10:52 ` Dmitry Baryshkov
2025-08-18 12:47 ` Michael Walle [this message]
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