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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2025 11:12:25.4023 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e9808eb-27dc-4a12-1635-08ddfced92ad X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA52.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4177 On Fri Sep 26, 2025 at 12:52 PM CEST, Jan Beulich wrote: > On 26.09.2025 12:38, Grygorii Strashko wrote: >> On 26.09.25 11:17, Jan Beulich wrote: >>> On 25.09.2025 21:55, Grygorii Strashko wrote: >>>> From: Grygorii Strashko >>>> >>>> The LAPIC LVTx registers have two RO bits: >>>> - all: Delivery Status (DS) bit 12 >>>> - LINT0/LINT1: Remote IRR Flag (RIR) bit 14. >>>> This bit is reserved for other LVTx regs with RAZ/WI access type (M= MIO), while >>>> WRMSR (guest_wrmsr_x2apic()) has appropiate checks for reserved bit= s >>>> (MBZ access type). >>> >>> Question is what the behavior is for writing the r/o (but not reserved)= bits. >>> I wasn't able to find any statement in the SDM. >>=20 >> Me too. Usually RO/WI on most HW. >> For example, LAPIC MMIO "Write" will be ignored (WRMSR will trigger exce= ption). > > My remark was specifically about WRMSR, and what you say here contradicts= ... Not quite what you're asking, but writing to the X2APIC_ID register does tr= igger #GP(0), so one would hope writing to RO bits triggers an exception too rath= er than being WI when mixed with RW bits in a register. Now again, it might not in order to avoid #GP(0) on a race. Definitely worth running a silly test with wrmsr_safe() to make sure. I cou= ld see real hardware going either way. Cheers, Alejandro