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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: TM7TQKvyQTZbe9s1Q1eCm/QOnFQmdygG+BrqiL6069AWJ8KPPXb+aqd9W9fW2kX4BTUZDK7eddqnFsHOIIBtj+FniJnuW429JPPhmoyL03LP6oikgtrNKthihFFmxrTT0OR+J8l2SeiFfJQsCKrSO6PdBfMzPEhYyLIyJnlDrzxxczR5p0QZ4tqk4rAXccuGUwMjs4+KRkK/xwlpW/ne3zJ5EzP7Pn7bqTBn4axvDV70QS6ypTNCTNVJZwBbaRZH22L4NvDY88ZX0YYNPlAK9eqiv5V4zgh9GqctTPmnkCFkqCDSZKOMU0SnvqM0VMq2I3d3hi/VYUcgjnwpTJ2ZWdN/dObPqqYnCnZfcaF0Io2oWasVjvMaMS+R3VTFnfOrlAG6TEzlaD/Ewy2+nMaL/+u27p1o0J8c4UhV6zvZgS6bUjBtQ/Y5lYLtdHLSR8Gb X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2026 15:28:03.0358 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 589f9c86-765a-45c8-2b84-08df1987422d X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D0A.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6603 X-purgate-ID: tlsNG-c201ff/1790177289-F4EA12A1-AD888603/0/0 X-purgate-type: clean X-purgate-size: 14912 Hi Mykola, Sorry for the delay to review this serie. > On 27 Aug 2026, at 16:31, Mykola Kvach wrote: >=20 > From: Mirela Simonovic >=20 > System suspend may lead to a state where GIC would be powered down. > Therefore, Xen should save/restore the context of GIC on suspend/resume. >=20 > Note that the context consists of states of registers which are > controlled by the hypervisor. Other GIC registers which are accessible > by guests are saved/restored on context switch. >=20 > Transient physical SGI pending state (GICD_CPENDSGIRn/GICD_SPENDSGIRn) > is intentionally excluded. CPU-interface active-priority state is also > not restored across suspend/resume. Xen reaches the final suspend path > at a quiescent point, so there is no active-priority execution context > to replay after resume. Enforce this with a runtime check after > disabling the CPU interface: if any implemented GICC_APRn word is still > non-zero, restore GICC_CTLR and abort suspend with -EBUSY. You mention SGI pending state but you do not say what would happen for PPI/= SPI pending state, and the patch does not look at or save/restore GICD_ISPENDR. Can you clarify what is expected for those? Cheers Bertrand >=20 > This does not apply to distributor active state. With GICv2 EOImode=3D=3D= 1, > EOIR only drops the interrupt priority; final deactivation is a separate > step. For guest-routed interrupts, Xen can have already EOIed the physica= l > IRQ while deactivation is still pending on the vGIC/GICV path. Therefore > GICD_ISACTIVER is preserved as architectural in-flight interrupt state. >=20 > Signed-off-by: Mirela Simonovic > Signed-off-by: Saeed Nowshadi > Signed-off-by: Mykyta Poturai > Signed-off-by: Mykola Kvach > Reviewed-by: Luca Fancellu > --- > Changes in V10: > - Limit GICC_APR active-priority checks to APR bits visible from > the Xen CPU-interface view. > - Avoid touching reserved GICD_IPRIORITYR/GICD_ITARGETSR words when the > last implemented interrupt block is partial. > - Restore distributor configuration before restoring interrupt enable > state, so GICD_ICFGR is written while the corresponding interrupts are > disabled. >=20 > Changes in V9: > - Skip saving/restoring GICD_ITARGETSR0..7 because SGI/PPI target > registers hold no state (read-only on MP, RAZ/WI on UP). > - Add a runtime GICC_APRn quiescence check after disabling the CPU > interface, and restore GICC_CTLR before returning -EBUSY. >=20 > Changes in V8: > - disable cpu interface + distributor before suspend > - change 0xffffffff to GENMASK; > - cosmetic changes; >=20 > Changes in V7: > - Allocate one contiguous memory block for the GICv2 dist suspend context= . > - gicv2_resume() no longer unconditionally re-enables the distributor/CPU > interface; it now writes back the saved CTLR values as-is. > - gicv2_alloc_context() now returns 0 on success and panics on failure, > since suspend context allocation is not recoverable. > --- > xen/arch/arm/gic-v2.c | 226 +++++++++++++++++++++++++++++++++ > xen/arch/arm/gic.c | 29 +++++ > xen/arch/arm/include/asm/gic.h | 12 ++ > 3 files changed, 267 insertions(+) >=20 > diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c > index 43a379fdda..a0ef6ffc7f 100644 > --- a/xen/arch/arm/gic-v2.c > +++ b/xen/arch/arm/gic-v2.c > @@ -1108,6 +1108,223 @@ static int gicv2_iomem_deny_access(struct domain = *d) > return iomem_deny_access(d, mfn, mfn + nr - 1); > } >=20 > +#ifdef CONFIG_SYSTEM_SUSPEND > + > +/* This struct represents block of 32 IRQs */ > +struct irq_block { > + uint32_t icfgr[2]; /* 2 registers of 16 IRQs each */ > + uint32_t ipriorityr[8]; > + uint32_t isenabler; > + uint32_t isactiver; > + uint32_t itargetsr[8]; > +}; > + > +/* GICv2 registers to be saved/restored on system suspend/resume */ > +struct gicv2_context { > + /* GICC context */ > + struct cpu_ctx { > + uint32_t ctlr; > + uint32_t pmr; > + uint32_t bpr; > + } cpu; > + > + /* GICD context */ > + struct dist_ctx { > + uint32_t ctlr; > + /* Includes banked SGI/PPI state for the boot CPU. */ > + struct irq_block *irqs; > + } dist; > +}; > + > +static struct gicv2_context gic_ctx; > + > +#define GICV2_NR_APRS 4 > +#define GICV2_APR_BITS_PER_REG 32U > + > +static int gicv2_check_active_priorities(uint32_t bpr) > +{ > + unsigned int i, apr_bits, nr_aprs; > + > + /* > + * Xen writes GICC_BPR to 0 during CPU init and does not change it. = Per > + * IHI0048B.b, a write below the implementation minimum reads back a= s the > + * minimum supported BPR value. Table 4-47 maps that Xen-visible BPR= value > + * to the visible GICC_APR bits. Avoid reading APR registers outs= ide > + * that visible range. > + * > + * This covers both GICv2 with and without Security Extensions. > + */ > + apr_bits =3D 1U << (7 - (bpr & 0x7)); > + nr_aprs =3D DIV_ROUND_UP(apr_bits, GICV2_APR_BITS_PER_REG); > + > + ASSERT(nr_aprs <=3D GICV2_NR_APRS); > + > + for ( i =3D 0; i < nr_aprs; i++ ) > + { > + unsigned int bits =3D min(GICV2_APR_BITS_PER_REG, > + apr_bits - i * GICV2_APR_BITS_PER_REG); > + uint32_t mask =3D GENMASK(bits - 1, 0); > + uint32_t apr =3D readl_gicc(GICC_APR + i * 4) & mask; > + > + if ( !apr ) > + continue; > + > + printk(XENLOG_ERR "GICv2: suspend aborted: GICC_APR%u=3D%#08x\n"= , > + i, apr); > + return -EBUSY; > + } > + > + return 0; > +} > + > +static int gicv2_suspend(void) > +{ > + unsigned int i, blocks =3D DIV_ROUND_UP(gicv2_info.nr_lines, 32); > + int ret; > + > + /* Save GICC_CTLR configuration. */ > + gic_ctx.cpu.ctlr =3D readl_gicc(GICC_CTLR); > + > + /* Quiesce the GIC CPU interface before suspend. */ > + gicv2_cpu_disable(); > + > + gic_ctx.cpu.bpr =3D readl_gicc(GICC_BPR); > + > + /* > + * Check the active-priority state for the group Xen drives through = the > + * CPU interface. GICC_CTL_ENABLE enables Group 0 without SecurityEx= tn and > + * Group 1 in Xen's Non-secure view with SecurityExtn, and in both c= ases > + * the relevant state is visible through GICC_APRn. The APR layout i= s > + * implementation-defined, so only test the bits visible from Xen's = CPU > + * interface view instead of reading every possible APR register. > + */ > + ret =3D gicv2_check_active_priorities(gic_ctx.cpu.bpr); > + if ( ret ) > + { > + writel_gicc(gic_ctx.cpu.ctlr, GICC_CTLR); > + return ret; > + } > + > + gic_ctx.cpu.pmr =3D readl_gicc(GICC_PMR); > + > + /* Save GICD configuration */ > + gic_ctx.dist.ctlr =3D readl_gicd(GICD_CTLR); > + writel_gicd(0, GICD_CTLR); > + > + for ( i =3D 0; i < blocks; i++ ) > + { > + struct irq_block *irqs =3D gic_ctx.dist.irqs + i; > + size_t j, off =3D i * sizeof(irqs->isenabler); > + size_t nr_regs =3D ARRAY_SIZE(irqs->ipriorityr); > + > + if ( i =3D=3D blocks - 1 ) > + nr_regs =3D DIV_ROUND_UP(gicv2_info.nr_lines - i * 32, 4); > + > + irqs->isenabler =3D readl_gicd(GICD_ISENABLER + off); > + > + /* > + * Save distributor active state as part of the hypervisor-owned > + * physical interrupt state. In GICv2 EOImode=3D=3D1, EOIR only = drops the > + * priority; final deactivation is separate. For guest-routed > + * interrupts, Xen may have EOIed the physical IRQ while the gue= st/vGIC > + * side still owns the deactivate step. Therefore GICD_ISACTIVER= can > + * legitimately remain set even though transient SGI pending sta= te and > + * CPU-interface active-priority state are expected to be quiesc= ed here. > + */ > + irqs->isactiver =3D readl_gicd(GICD_ISACTIVER + off); > + > + off =3D i * sizeof(irqs->ipriorityr); > + for ( j =3D 0; j < nr_regs; j++ ) > + irqs->ipriorityr[j] =3D readl_gicd(GICD_IPRIORITYR + off + j= * 4); > + > + /* > + * GICD_ITARGETSR0..7 cover SGIs/PPIs and hold no state to save: > + * they are read-only on multiprocessor implementations and RAZ/= WI > + * on uniprocessor implementations. > + */ > + if ( i ) > + { > + off =3D i * sizeof(irqs->itargetsr); > + for ( j =3D 0; j < nr_regs; j++ ) > + irqs->itargetsr[j] =3D readl_gicd(GICD_ITARGETSR + off += j * 4); > + } > + > + off =3D i * sizeof(irqs->icfgr); > + for ( j =3D 0; j < ARRAY_SIZE(irqs->icfgr); j++ ) > + irqs->icfgr[j] =3D readl_gicd(GICD_ICFGR + off + j * 4); > + } > + > + return 0; > +} > + > +static void gicv2_resume(void) > +{ > + unsigned int i, blocks =3D DIV_ROUND_UP(gicv2_info.nr_lines, 32); > + > + gicv2_cpu_disable(); > + /* Disable distributor */ > + writel_gicd(0, GICD_CTLR); > + > + for ( i =3D 0; i < blocks; i++ ) > + { > + struct irq_block *irqs =3D gic_ctx.dist.irqs + i; > + size_t j, off =3D i * sizeof(irqs->isenabler); > + size_t nr_regs =3D ARRAY_SIZE(irqs->ipriorityr); > + > + if ( i =3D=3D blocks - 1 ) > + nr_regs =3D DIV_ROUND_UP(gicv2_info.nr_lines - i * 32, 4); > + > + writel_gicd(GENMASK(31, 0), GICD_ICENABLER + off); > + > + off =3D i * sizeof(irqs->icfgr); > + for ( j =3D 0; j < ARRAY_SIZE(irqs->icfgr); j++ ) > + writel_gicd(irqs->icfgr[j], GICD_ICFGR + off + j * 4); > + > + off =3D i * sizeof(irqs->ipriorityr); > + for ( j =3D 0; j < nr_regs; j++ ) > + writel_gicd(irqs->ipriorityr[j], GICD_IPRIORITYR + off + j *= 4); > + > + /* > + * GICD_ITARGETSR0..7 cover SGIs/PPIs and hold no state to save: > + * they are read-only on multiprocessor implementations and RAZ/= WI > + * on uniprocessor implementations. > + */ > + if ( i ) > + { > + off =3D i * sizeof(irqs->itargetsr); > + for ( j =3D 0; j < nr_regs; j++ ) > + writel_gicd(irqs->itargetsr[j], GICD_ITARGETSR + off + j= * 4); > + } > + > + off =3D i * sizeof(irqs->isenabler); > + writel_gicd(irqs->isenabler, GICD_ISENABLER + off); > + > + writel_gicd(GENMASK(31, 0), GICD_ICACTIVER + off); > + writel_gicd(irqs->isactiver, GICD_ISACTIVER + off); > + } > + > + /* Restore distributor control state. */ > + writel_gicd(gic_ctx.dist.ctlr, GICD_CTLR); > + > + /* Restore GIC CPU interface configuration */ > + writel_gicc(gic_ctx.cpu.pmr, GICC_PMR); > + writel_gicc(gic_ctx.cpu.bpr, GICC_BPR); > + > + /* Enable GIC CPU interface */ > + writel_gicc(gic_ctx.cpu.ctlr, GICC_CTLR); > +} > + > +static void __init gicv2_alloc_context(void) > +{ > + uint32_t blocks =3D DIV_ROUND_UP(gicv2_info.nr_lines, 32); > + > + gic_ctx.dist.irqs =3D xzalloc_array(struct irq_block, blocks); > + if ( !gic_ctx.dist.irqs ) > + panic("Failed to allocate memory for GICv2 suspend context\n"); > +} > + > +#endif /* CONFIG_SYSTEM_SUSPEND */ > + > #ifdef CONFIG_ACPI > static unsigned long gicv2_get_hwdom_extra_madt_size(const struct domain = *d) > { > @@ -1312,6 +1529,11 @@ static int __init gicv2_init(void) >=20 > spin_unlock(&gicv2.lock); >=20 > +#ifdef CONFIG_SYSTEM_SUSPEND > + /* Allocate memory to be used for saving GIC context during the susp= end */ > + gicv2_alloc_context(); > +#endif /* CONFIG_SYSTEM_SUSPEND */ > + > return 0; > } >=20 > @@ -1355,6 +1577,10 @@ static const struct gic_hw_operations gicv2_ops = =3D { > .map_hwdom_extra_mappings =3D gicv2_map_hwdom_extra_mappings, > .iomem_deny_access =3D gicv2_iomem_deny_access, > .do_LPI =3D gicv2_do_LPI, > +#ifdef CONFIG_SYSTEM_SUSPEND > + .suspend =3D gicv2_suspend, > + .resume =3D gicv2_resume, > +#endif /* CONFIG_SYSTEM_SUSPEND */ > }; >=20 > /* Set up the GIC */ > diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c > index 078049e741..ffc11f36a1 100644 > --- a/xen/arch/arm/gic.c > +++ b/xen/arch/arm/gic.c > @@ -438,6 +438,35 @@ int gic_iomem_deny_access(struct domain *d) > return gic_hw_ops->iomem_deny_access(d); > } >=20 > +#ifdef CONFIG_SYSTEM_SUSPEND > + > +int gic_suspend(void) > +{ > + /* Must be called by boot CPU#0 with interrupts disabled */ > + ASSERT(!local_irq_is_enabled()); > + ASSERT(!smp_processor_id()); > + > + if ( !gic_hw_ops->suspend || !gic_hw_ops->resume ) > + return -ENOSYS; > + > + return gic_hw_ops->suspend(); > +} > + > +void gic_resume(void) > +{ > + /* > + * Must be called by boot CPU#0 with interrupts disabled after gic_s= uspend > + * has returned successfully. > + */ > + ASSERT(!local_irq_is_enabled()); > + ASSERT(!smp_processor_id()); > + ASSERT(gic_hw_ops->resume); > + > + gic_hw_ops->resume(); > +} > + > +#endif /* CONFIG_SYSTEM_SUSPEND */ > + > static int cpu_gic_callback(struct notifier_block *nfb, > unsigned long action, > void *hcpu) > diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gi= c.h > index ee2c26adb4..29bb9a89a4 100644 > --- a/xen/arch/arm/include/asm/gic.h > +++ b/xen/arch/arm/include/asm/gic.h > @@ -301,6 +301,12 @@ extern int gicv_setup(struct domain *d); > extern void gic_save_state(struct vcpu *v); > extern void gic_restore_state(struct vcpu *v); >=20 > +#ifdef CONFIG_SYSTEM_SUSPEND > +/* Suspend/resume */ > +extern int gic_suspend(void); > +extern void gic_resume(void); > +#endif /* CONFIG_SYSTEM_SUSPEND */ > + > /* SGI (AKA IPIs) */ > enum gic_sgi { > GIC_SGI_EVENT_CHECK, > @@ -444,6 +450,12 @@ struct gic_hw_operations { > int (*iomem_deny_access)(struct domain *d); > /* Handle LPIs, which require special handling */ > void (*do_LPI)(unsigned int lpi); > +#ifdef CONFIG_SYSTEM_SUSPEND > + /* Save GIC configuration due to the system suspend */ > + int (*suspend)(void); > + /* Restore GIC configuration due to the system resume */ > + void (*resume)(void); > +#endif /* CONFIG_SYSTEM_SUSPEND */ > }; >=20 > extern const struct gic_hw_operations *gic_hw_ops; > --=20 > 2.43.0 >=20