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Wed, 08 Oct 2025 23:47:28 -0700 (PDT) Received: from localhost ([193.86.240.59]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-4255d8e97f0sm32843535f8f.27.2025.10.08.23.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Oct 2025 23:47:27 -0700 (PDT) Mime-Version: 1.0 Date: Thu, 09 Oct 2025 08:47:27 +0200 Message-Id: From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= Subject: Re: [PATCH v4 3/3] RISC-V: Add support for srmcfg CSR from Ssqosid ext Cc: "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Alexandre Ghiti" , "Conor Dooley" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , =?utf-8?q?Kornel_Dul=C4=99ba?= , "Adrien Ricciardi" , "James Morse" , "Atish Kumar Patra" , "Atish Patra" , "Vasudevan Srinivasan" , "Conor Dooley" , , , , , , "linux-riscv" To: "Drew Fustini" References: <20251007-ssqosid-v4-0-e8b57e59d812@kernel.org> <20251007-ssqosid-v4-3-e8b57e59d812@kernel.org> In-Reply-To: <20251007-ssqosid-v4-3-e8b57e59d812@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251008_234730_186784_587F35EF X-CRM114-Status: UNSURE ( 6.64 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org 2025-10-07T23:21:12-07:00, Drew Fustini : > diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h > +static inline void __switch_to_srmcfg(struct task_struct *next) > +{ > + u32 *cpu_srmcfg_ptr = this_cpu_ptr(&cpu_srmcfg); > + u32 thread_srmcfg; > + > + thread_srmcfg = READ_ONCE(next->thread.srmcfg); > + > + if (thread_srmcfg != *cpu_srmcfg_ptr) { Wouldn't prev->thread.srmcfg have the value of CSR_SRMCFG when executing switch_to? Thanks. > + *cpu_srmcfg_ptr = thread_srmcfg; > + csr_write(CSR_SRMCFG, thread_srmcfg); > + } > +} _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CA9F211290 for ; Thu, 9 Oct 2025 06:47:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759992451; cv=none; b=Yt/SDirfbVfQh6M37oiZLdkLdO6WxyXoOCALXqsODX3AEuCwC6305NhI9AXBbLQZGh6vFsc/3zobHbphu4fjlKw+jFVVSjQcYOGNm08TXWk28w81IOUJF+fcXoapDRukxr+Jh4OzERL6jN14k6YgjJ9K17kBa9wd0e/PxqnW7mI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; 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Wed, 08 Oct 2025 23:47:28 -0700 (PDT) Received: from localhost ([193.86.240.59]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-4255d8e97f0sm32843535f8f.27.2025.10.08.23.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Oct 2025 23:47:27 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 09 Oct 2025 08:47:27 +0200 Message-Id: From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= Subject: Re: [PATCH v4 3/3] RISC-V: Add support for srmcfg CSR from Ssqosid ext Cc: "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Alexandre Ghiti" , "Conor Dooley" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , =?utf-8?q?Kornel_Dul=C4=99ba?= , "Adrien Ricciardi" , "James Morse" , "Atish Kumar Patra" , "Atish Patra" , "Vasudevan Srinivasan" , "Conor Dooley" , , , , , , "linux-riscv" To: "Drew Fustini" References: <20251007-ssqosid-v4-0-e8b57e59d812@kernel.org> <20251007-ssqosid-v4-3-e8b57e59d812@kernel.org> In-Reply-To: <20251007-ssqosid-v4-3-e8b57e59d812@kernel.org> 2025-10-07T23:21:12-07:00, Drew Fustini : > diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h > +static inline void __switch_to_srmcfg(struct task_struct *next) > +{ > + u32 *cpu_srmcfg_ptr =3D this_cpu_ptr(&cpu_srmcfg); > + u32 thread_srmcfg; > + > + thread_srmcfg =3D READ_ONCE(next->thread.srmcfg); > + > + if (thread_srmcfg !=3D *cpu_srmcfg_ptr) { Wouldn't prev->thread.srmcfg have the value of CSR_SRMCFG when executing switch_to? Thanks. > + *cpu_srmcfg_ptr =3D thread_srmcfg; > + csr_write(CSR_SRMCFG, thread_srmcfg); > + } > +}