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Wed, 22 Oct 2025 06:47:34 +0000 Received: from CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989]) by CH2PR12MB3990.namprd12.prod.outlook.com ([fe80::7de1:4fe5:8ead:5989%6]) with mapi id 15.20.9253.011; Wed, 22 Oct 2025 06:47:34 +0000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 22 Oct 2025 15:47:30 +0900 Message-Id: Cc: "Alistair Popple" , "Miguel Ojeda" , "Alex Gaynor" , "Boqun Feng" , "Gary Guo" , , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "John Hubbard" , "Timur Tabi" , , "Elle Rhumsaa" , "Daniel Almeida" , Subject: Re: [PATCH 5/7] gpu: nova-core: Add support for managing GSP falcon interrupts From: "Alexandre Courbot" To: "Joel Fernandes" , , , , , X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20251020185539.49986-1-joelagnelf@nvidia.com> <20251020185539.49986-6-joelagnelf@nvidia.com> In-Reply-To: <20251020185539.49986-6-joelagnelf@nvidia.com> X-ClientProxiedBy: TYWPR01CA0022.jpnprd01.prod.outlook.com (2603:1096:400:aa::9) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|LV8PR12MB9408:EE_ X-MS-Office365-Filtering-Correlation-Id: 87a183a7-2494-4bae-5577-08de1136e12d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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These are required for > GSP message queue interrupt handling. > > Also rename clear_swgen0_intr() to enable_msq_interrupt() for > readability. Let's make this "also" its own patch as it is a different thing. > > Signed-off-by: Joel Fernandes > --- > drivers/gpu/nova-core/falcon/gsp.rs | 26 +++++++++++++++++++++++--- > drivers/gpu/nova-core/gpu.rs | 2 +- > drivers/gpu/nova-core/regs.rs | 10 ++++++++++ > 3 files changed, 34 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/= falcon/gsp.rs > index f17599cb49fa..6da63823996b 100644 > --- a/drivers/gpu/nova-core/falcon/gsp.rs > +++ b/drivers/gpu/nova-core/falcon/gsp.rs > @@ -22,11 +22,31 @@ impl FalconEngine for Gsp { > } > =20 > impl Falcon { > - /// Clears the SWGEN0 bit in the Falcon's IRQ status clear register = to > - /// allow GSP to signal CPU for processing new messages in message q= ueue. > - pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) { > + /// Enable the GSP Falcon message queue interrupt (SWGEN0 interrupt)= . > + #[expect(dead_code)] > + pub(crate) fn enable_msgq_interrupt(&self, bar: &Bar0) { > + regs::NV_PFALCON_FALCON_IRQMASK::alter(bar, &Gsp::ID, |r| r.set_= swgen0(true)); > + } > + > + /// Check if the message queue interrupt is pending. > + #[expect(dead_code)] > + pub(crate) fn has_msgq_interrupt(&self, bar: &Bar0) -> bool { > + regs::NV_PFALCON_FALCON_IRQSTAT::read(bar, &Gsp::ID).swgen0() > + } > + > + /// Clears the message queue interrupt to allow GSP to signal CPU > + /// for processing new messages. > + pub(crate) fn clear_msgq_interrupt(&self, bar: &Bar0) { > regs::NV_PFALCON_FALCON_IRQSCLR::default() > .set_swgen0(true) > .write(bar, &Gsp::ID); > } > + > + /// Acknowledge all pending GSP interrupts. > + #[expect(dead_code)] > + pub(crate) fn ack_all_interrupts(&self, bar: &Bar0) { > + // Read status and write the raw value to IRQSCLR to clear all p= ending interrupts. > + let status =3D regs::NV_PFALCON_FALCON_IRQSTAT::read(bar, &Gsp::= ID); > + regs::NV_PFALCON_FALCON_IRQSCLR::from(u32::from(status)).write(b= ar, &Gsp::ID); > + } I think this can be a bit more generic than that: all interrupts for all falcons are handled the same way, so we shouldn't need to write `enable`, `clear`, and other methods for each. So the first step should probably be a generic `impl Falcon` block that provides base methods for specialized blocks to reuse. It could work with just the index of the bit corresponding to the interrupt to enable/clear, but if we want to involve the type system we could also define a `FalconInterrupt` trait with an associated type for the engine on which this interrupt is valid, and its bit index as an associated const. But I suspect that the set of interrupts is going to be pretty standard, so maybe we can use the standard nomenclature for the generic methods (i.e. SWGEN0), and have dedicated methods for specialized units where relevant.