On Thu Oct 23, 2025 at 3:50 PM CEST, Udit Kumar wrote:
> Hi Michael,
>
> On 10/17/2025 3:52 PM, Michael Walle wrote:
>> At the moment the clock parent of the audio extclk output is PLL1_HSDIV6
>> of the main domain. This very clock output is also used among various IP
>> cores, for example for the USB1 LPM clock. The audio extclock being an
>> external clock output with a variable frequency, it is likely that a
>> user of this clock will try to set it's frequency to a different value,
>> i.e. an audio codec. Because that clock output is used also for other IP
>> cores, bad things will happen.
>>
>> Instead of using PLL1_HSDIV6 use the PLL2_HSDIV8 as a sane default, as
>> this output is exclusively used among other audio peripherals.
>
>
> Thanks for this fix,
>
> Initial support for audio_refclkx was added in j722s and am62p soc 
> specific files due
>
> to selection of different parent.
>
> Since these SOC share many common things, and this patch will make these 
> nodes same as of am62p device
>
> https://elixir.bootlin.com/linux/v6.18-rc2/source/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi#L46 
>
>
> So I suggest to move in common file 
> https://elixir.bootlin.com/linux/v6.18-rc2/source/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi#L42 
>
>
> and remove from SOC specific files.

Ok, but to keep the information and to not conflate two different
things, I'd do the following:
 - keep this patch as is
 - add a second one, to move the (now) identical nodes into the
   common-main.dtsi

Sounds good?

-michael