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Cc: "opensbi" To: "Benedikt Freisen" , From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20251026202416.23550-1-b.freisen@gmx.net> <20251026202416.23550-3-b.freisen@gmx.net> In-Reply-To: <20251026202416.23550-3-b.freisen@gmx.net> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251027_041654_977400_18EE30D0 X-CRM114-Status: GOOD ( 12.84 ) X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "opensbi" Errors-To: opensbi-bounces+opensbi=archiver.kernel.org@lists.infradead.org 2025-10-26T21:21:56+01:00, Benedikt Freisen : > According to the RISCVuzz paper by Thomas et al., the T-Head/Xuantie C906 > and C910 cores fail to ignore reserved fields in the "fence" and "fence.i" > encodings and trigger illegal instruction traps if these fields are non-zero, > so address that in the illegal instruction trap handler. > > Signed-off-by: Benedikt Freisen > --- > diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h > @@ -944,8 +944,12 @@ > +#define INSN_MASK_FENCE 0xf000707f Bits 31, 30, 29, and 28 should not be a part of the mask, because any reserved value there must be treated as 0b0000. > +#define INSN_MATCH_FENCE 0x0000000f > #define INSN_MASK_FENCE_TSO 0xffffffff (Related: INSN_MASK_FENCE_TSO should ignore the reserved rs1/rd fields, but covering that encoding with the new IORW fence is acceptable.) > #define INSN_MATCH_FENCE_TSO 0x8330000f > +#define INSN_MASK_FENCE_I 0x0000707f > +#define INSN_MATCH_FENCE_I 0x0000100f > diff --git a/lib/sbi/sbi_illegal_insn.c b/lib/sbi/sbi_illegal_insn.c > @@ -42,6 +42,21 @@ static int misc_mem_opcode_insn(ulong insn, struct sbi_trap_regs *regs) > + /* Errata workaround: C906, C910 fail to ignore reserved fields > + * in the `fence` and `fence.i` encodings. [Thomas2024RISCVuzz] */ > + if ((insn & INSN_MASK_FENCE) == INSN_MATCH_FENCE) { > + /* NOTE: Emulation should ideally preserve the `pred` and > + * `succ` fields, but that is not easily possible here. */ > + mb(); > + regs->mepc += 4; > + return 0; > + } > + if ((insn & INSN_MASK_FENCE_I) == INSN_MATCH_FENCE_I) { > + RISCV_FENCE_I; > + regs->mepc += 4; > + return 0; > + } Don't we want to hide these workarounds behind a config, so the code doesn't have to be included in builds for other platorms? Thanks. -- opensbi mailing list opensbi@lists.infradead.org http://lists.infradead.org/mailman/listinfo/opensbi