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Tue, 18 Nov 2025 05:42:35 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::3052]) by smtp.gmail.com with UTF8SMTPSA id a640c23a62f3a-b734fd80841sm1362757766b.41.2025.11.18.05.42.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Nov 2025 05:42:34 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 18 Nov 2025 14:42:09 +0100 Message-Id: Subject: Re: [PATCH 2/3] target/riscv: Fix pointer masking PMM field selection logic Cc: "Palmer Dabbelt" , "Alistair Francis" , "Weiwei Li" , "Daniel Henrique Barboza" , "Liu Zhiwei" , "open list:RISC-V TCG CPUs" , To: , From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20251118105936.2839054-1-frank.chang@sifive.com> <20251118105936.2839054-3-frank.chang@sifive.com> In-Reply-To: <20251118105936.2839054-3-frank.chang@sifive.com> Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=rkrcmar@ventanamicro.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org 2025-11-18T18:59:35+08:00, : > From: Frank Chang > > mstatus.MPV only records the previous virtualization state, and does not > affect pointer masking according to the Zjpm specification. > > This patch rewrites riscv_pm_get_pmm() to follow the architectural > definition of Smmpm, Smnpm, and Ssnpm. > > The resulting PMM source for each mode is summarized below: > > * Smmpm + Smnpm + Ssnpm: > M-mode: mseccfg.PMM > S-mode: menvcfg.PMM > U-mode: senvcfg.PMM > VS-mode: henvcfg.PMM > VU-mode: senvcfg.PMM > > * Smmpm + Smnpm (RVS implemented): > M-mode: mseccfg.PMM > S-mode: menvcfg.PMM > U/VS/VU: disabled (Ssnpm not present) > > * Smmpm + Smnpm (RVS not implemented): > M-mode: mseccfg.PMM > U-mode: menvcfg.PMM > S/VS/VU: disabled (no S-mode) > > * Smmpm only: > M-mode: mseccfg.PMM > Other existing modes: pointer masking disabled > > Signed-off-by: Frank Chang > --- > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > @@ -154,22 +154,30 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) > } > break; > case PRV_S: > - if (riscv_cpu_cfg(env)->ext_smnpm) { > - if (get_field(env->mstatus, MSTATUS_MPV)) { > - return get_field(env->henvcfg, HENVCFG_PMM); > - } else { > + if (!env->virt_enabled) { > + if (riscv_cpu_cfg(env)->ext_smnpm) { It wasn't correct before, but it doesn't seem correct now either. MPRV+MPV+MPP change the effective access mode to VS without setting virt_enabled, and henvcfg is supposed to be used in that case. I liked the way you described the desired behavior in the commit message: M-mode: mseccfg.PMM S-mode: menvcfg.PMM U-mode: senvcfg.PMM VS-mode: henvcfg.PMM VU-mode: senvcfg.PMM Can we have a "switch (get_effective_access_mode(env))" with the same structure? Thanks. --- Other bugs I noticed while skimming the adjust_addr_body() and riscv_pm_get_pmm(): * Sign extension for HLV/HSV must be performed when vsatp.MODE !=3D Bare. * The sign extension also depends on the effective mode, and not on the current mode. * MXR should set PMLEN=3D0 for all accesses that aren't M to M, not just when using MPRV.