From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Drew Fustini" <fustini@kernel.org>, <qemu-devel@nongnu.org>
Cc: "Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Weiwei Li" <liwei1518@gmail.com>,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
qemu-riscv@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Nicolas Pitre" <npitre@baylibre.com>,
"Kornel Dulęba" <mindal@semihalf.com>,
"Atish Kumar Patra" <atishp@rivosinc.com>,
"Atish Patra" <atish.patra@linux.dev>,
"Vasudevan Srinivasan" <vasu@rivosinc.com>,
"yunhui cui" <cuiyunhui@bytedance.com>,
"Chen Pei" <cp0613@linux.alibaba.com>,
guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn,
qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org
Subject: Re: [PATCH 1/7] riscv: implement Ssqosid extension and srmcfg CSR
Date: Thu, 20 Nov 2025 17:07:03 +0100 [thread overview]
Message-ID: <DEDNGGQCPNKP.25HNT2IHYB0C2@ventanamicro.com> (raw)
In-Reply-To: <20251119-riscv-ssqosid-cbqri-v1-1-3392fc760e48@kernel.org>
2025-11-19T16:42:17-08:00, Drew Fustini <fustini@kernel.org>:
> From: Kornel Dulęba <mindal@semihalf.com>
>
> Implement the srmcfg CSR defined by the Ssqosid ISA extension
> (Supervisor-mode Quality of Service ID). The CSR contains two fields:
>
> - Resource Control ID (RCID) used determine resource allocation
> - Monitoring Counter ID (MCID) used to track resource usage
>
> The CSR is defined for S-mode but accessing it when V=1 shall cause a
> virtual instruction exception. Implement this behavior by calling the
> hmode predicate.
>
> Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/download/v1.0/riscv-cbqri.pdf
> Signed-off-by: Kornel Dulęba <mindal@semihalf.com>
> [fustini: rebase on v10.1.50, fix check_srmcfg]
> Signed-off-by: Drew Fustini <fustini@kernel.org>
> ---
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> @@ -216,6 +216,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(ssdbltrp, PRIV_VERSION_1_13_0, ext_ssdbltrp),
> ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm),
> ISA_EXT_DATA_ENTRY(sspm, PRIV_VERSION_1_13_0, ext_sspm),
> + ISA_EXT_DATA_ENTRY(ssqosid, PRIV_VERSION_1_12_0, ext_ssqosid),
Just out of curiosity, where does PRIV_VERSION_1_12_0 come from?
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> @@ -1759,6 +1759,37 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
> +static RISCVException check_srmcfg(CPURISCVState *env, int csrno)
> +{
> + RISCVCPU *cpu = env_archcpu(env);
> +
> + if (!cpu->cfg.ext_ssqosid) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + /*
> + * Even though this is an S-mode CSR the spec says that we need to throw
> + * and virt instruction fault if a guest tries to access it.
> + */
> + return env->virt_enabled ?
> + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : smode(env, csrno);
> +}
The check is missing interaction with mstateen0.SRMCFG.
Thanks.
next prev parent reply other threads:[~2025-11-20 16:08 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-20 0:42 [PATCH 0/7] riscv: implement Ssqosid extension and CBQRI controllers Drew Fustini
2025-11-20 0:42 ` [PATCH 1/7] riscv: implement Ssqosid extension and srmcfg CSR Drew Fustini
2025-11-20 11:30 ` Daniel Henrique Barboza
2025-11-20 21:34 ` Drew Fustini
2025-11-20 16:07 ` Radim Krčmář [this message]
2025-11-20 20:46 ` Drew Fustini
2025-11-24 16:54 ` Radim Krčmář
2025-11-20 0:42 ` [PATCH 2/7] hw/riscv: define capabilities of CBQRI controllers Drew Fustini
2025-11-20 11:59 ` Daniel Henrique Barboza
2025-11-20 0:42 ` [PATCH 3/7] hw/riscv: implement CBQRI capacity controller Drew Fustini
2025-11-20 11:47 ` Daniel Henrique Barboza
2025-11-21 18:57 ` Drew Fustini
2025-11-20 19:25 ` Radim Krčmář
2025-11-21 19:50 ` Drew Fustini
2025-11-24 17:02 ` Radim Krčmář
2025-11-24 18:37 ` Drew Fustini
2025-11-25 11:55 ` Radim Krčmář
2025-11-20 0:42 ` [PATCH 4/7] hw/riscv: implement CBQRI bandwidth controller Drew Fustini
2025-11-20 11:51 ` Daniel Henrique Barboza
2025-11-24 17:06 ` Radim Krčmář
2025-11-24 18:45 ` Drew Fustini
2025-11-20 0:42 ` [PATCH 5/7] hw/riscv: Kconfig: add CBQRI options Drew Fustini
2025-11-20 0:42 ` [PATCH 6/7] hw/riscv: meson: add CBQRI controllers to the build Drew Fustini
2025-11-20 12:01 ` Daniel Henrique Barboza
2025-11-20 20:56 ` Drew Fustini
2025-11-20 0:42 ` [PATCH 7/7] hw/riscv: add CBQRI controllers to virt machine Drew Fustini
2025-11-20 12:01 ` Daniel Henrique Barboza
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