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Mon, 24 Nov 2025 09:06:56 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::3052]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-477bf227ae2sm205686545e9.9.2025.11.24.09.06.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Nov 2025 09:06:55 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 24 Nov 2025 18:06:21 +0100 Message-Id: Subject: Re: [PATCH 4/7] hw/riscv: implement CBQRI bandwidth controller Cc: "Palmer Dabbelt" , "Alistair Francis" , "Weiwei Li" , "Daniel Henrique Barboza" , "Liu Zhiwei" , , "Paolo Bonzini" , "Nicolas Pitre" , =?utf-8?q?Kornel_Dul=C4=99ba?= , "Atish Kumar Patra" , "Atish Patra" , "Vasudevan Srinivasan" , "yunhui cui" , "Chen Pei" , , , To: "Drew Fustini" , From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20251119-riscv-ssqosid-cbqri-v1-0-3392fc760e48@kernel.org> <20251119-riscv-ssqosid-cbqri-v1-4-3392fc760e48@kernel.org> In-Reply-To: <20251119-riscv-ssqosid-cbqri-v1-4-3392fc760e48@kernel.org> Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=rkrcmar@ventanamicro.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org 2025-11-19T16:42:20-08:00, Drew Fustini : > From: Nicolas Pitre > > Implement a bandwidth controller according to the Capacity and Bandwidth > QoS Register Interface (CBQRI) which supports these capabilities: > > - Number of access types: 2 (code and data) > - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER > - Event IDs supported: None, Total read/write byte count, Total > read byte count, Total write byte count > - Bandwidth allocation operations: CONFIG_LIMIT, READ_LIMIT > > Link: https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.= pdf > Signed-off-by: Nicolas Pitre > [fustini: add fields introduced in the ratified spec: rpfx and p] > Signed-off-by: Drew Fustini > --- > diff --git a/hw/riscv/cbqri_bandwidth.c b/hw/riscv/cbqri_bandwidth.c > +static uint32_t bandwidth_config(RiscvCbqriBandwidthState *bc, > + uint32_t rcid, uint32_t at, > + bool *busy) > +{ > + BandwidthAllocation *bw_alloc =3D get_bw_alloc(bc, rcid, at); > + > + /* for now we only preserve the current BC_BW_ALLOC register content= */ There are a few checks that we could do even without any real accounting, like rbwb > 0, and sum_{rcid}(rcid.rbwb) <=3D mrbwb. Doing so might help us find some bugs in the software management layer. What is the level of ISA correctness that you're aiming for? (I'll tone down my review if nitpicks like that are not needed.) Thanks.