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Tue, 25 Nov 2025 07:26:20 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::3052]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-477bf1f365fsm258826945e9.8.2025.11.25.07.26.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Nov 2025 07:26:20 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 25 Nov 2025 16:25:45 +0100 Message-Id: Subject: Re: [PATCH v2 3/6] target/riscv: Fix pointer masking PMM field selection logic Cc: "Palmer Dabbelt" , "Alistair Francis" , "Weiwei Li" , "Daniel Henrique Barboza" , "Liu Zhiwei" , "open list:RISC-V TCG CPUs" , To: , From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20251121050413.3718427-1-frank.chang@sifive.com> <20251121050413.3718427-4-frank.chang@sifive.com> In-Reply-To: <20251121050413.3718427-4-frank.chang@sifive.com> Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=rkrcmar@ventanamicro.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 2025-11-21T13:04:10+08:00, : > From: Frank Chang > > mstatus.MPV only records the previous virtualization state, and does not > affect pointer masking according to the Zjpm specification. > > This patch rewrites riscv_pm_get_pmm() to follow the architectural > definition of Smmpm, Smnpm, and Ssnpm. > > The resulting PMM selection logic for each mode is summarized below: > > * mstatus.MXR =3D 1: pointer masking disabled > > * Smmpm + Smnpm + Ssnpm: > M-mode: mseccfg.PMM > S-mode: menvcfg.PMM > U-mode: senvcfg.PMM > VS-mode: henvcfg.PMM > VU-mode: senvcfg.PMM > > * Smmpm + Smnpm (RVS implemented): > M-mode: mseccfg.PMM > S-mode: menvcfg.PMM > U/VS/VU: disabled (Ssnpm not present) > > * Smmpm + Smnpm (RVS not implemented): > M-mode: mseccfg.PMM > U-mode: menvcfg.PMM > S/VS/VU: disabled (no S-mode) > > * Smmpm only: > M-mode: mseccfg.PMM > Other existing modes: pointer masking disabled > > Signed-off-by: Frank Chang > Reviewed-by: Daniel Henrique Barboza > --- > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) > { > #ifndef CONFIG_USER_ONLY > - int priv_mode =3D cpu_address_mode(env); > + int priv_mode; > + bool virt; > =20 > - if (get_field(env->mstatus, MSTATUS_MPRV) && > - get_field(env->mstatus, MSTATUS_MXR)) { > + if (get_field(env->mstatus, MSTATUS_MXR)) { > return PMM_FIELD_DISABLED; > } MSTATUS_MXR doesn't disable Pointer masking in M-mode, and we also need to consider virt, where vsstatus.MXR is in effect as well. > =20 > + riscv_cpu_eff_priv(env, &priv_mode, &virt); I think you could put something like this here: if ((mode !=3D PRV_M && get_field(env->mstatus, MSTATUS_MXR)) || (virt && get_field(env->vsstatus, MSTATUS_MXR))) { return PMM_FIELD_DISABLED; } > /* Get current PMM field */ > switch (priv_mode) { > case PRV_M: > @@ -189,22 +222,30 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) > case PRV_U: > - if (riscv_has_ext(env, RVS)) { > + if (!virt) { > if (riscv_cpu_cfg(env)->ext_ssnpm) { > return get_field(env->senvcfg, SENVCFG_PMM); > } > - } else { > + > if (riscv_cpu_cfg(env)->ext_smnpm) { > - return get_field(env->menvcfg, MENVCFG_PMM); > + if (!riscv_has_ext(env, RVS)) { > + return get_field(env->menvcfg, MENVCFG_PMM); > + } > + } > + } else { > + if (riscv_cpu_cfg(env)->ext_ssnpm) { > + return get_field(env->senvcfg, SENVCFG_PMM); > } > } virt doesn't really matter, the original code was correct. Thanks.