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Tue, 25 Nov 2025 07:41:50 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::3052]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-42cb7fb9190sm34926895f8f.33.2025.11.25.07.41.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Nov 2025 07:41:49 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 25 Nov 2025 16:41:14 +0100 Message-Id: Subject: Re: [PATCH v2 6/6] target/riscv: Fix pointer masking translation mode check bug Cc: "Palmer Dabbelt" , "Alistair Francis" , "Weiwei Li" , "Daniel Henrique Barboza" , "Liu Zhiwei" , "open list:RISC-V TCG CPUs" , To: , From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20251121050413.3718427-1-frank.chang@sifive.com> <20251121050413.3718427-7-frank.chang@sifive.com> In-Reply-To: <20251121050413.3718427-7-frank.chang@sifive.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=rkrcmar@ventanamicro.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 2025-11-21T13:04:13+08:00, : > From: Frank Chang > > When running with virtualization in VS/VU mode, or when executing the > virtual-machine load/store instructions (HLV.* and HSV.*), the type of > address that determines which pointer masking rules apply should be > checked against vsatp rather than satp. > > As a result, sign extension also applies to the virtual-machine > load/store instructions. > > Signed-off-by: Frank Chang > --- > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > @@ -286,16 +286,27 @@ RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *= env) > #endif > } > =20 > -bool riscv_cpu_virt_mem_enabled(CPURISCVState *env) > +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env, bool is_vm_ldst) > { > #ifndef CONFIG_USER_ONLY > int satp_mode =3D 0; > - int priv_mode =3D cpu_address_mode(env); > + uint64_t satp; > + int priv_mode; > + bool virt =3D false; > + > + if (!is_vm_ldst) { > + riscv_cpu_eff_priv(env, &priv_mode, &virt); > + } else { > + priv_mode =3D get_field(env->hstatus, HSTATUS_SPVP); > + virt =3D true; > + } > + > + satp =3D virt ? env->vsatp : env->satp; > =20 > if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { > - satp_mode =3D get_field(env->satp, SATP32_MODE); > + satp_mode =3D get_field(satp, SATP32_MODE); > } else { > - satp_mode =3D get_field(env->satp, SATP64_MODE); > + satp_mode =3D get_field(satp, SATP64_MODE); > } > =20 > return ((satp_mode !=3D VM_1_10_MBARE) && (priv_mode !=3D PRV_M)); riscv_cpu_virt_mem_enabled looked generic, so I got scared at the beginning, but it's luckily only used for pointer masking. Reviewed-by: Radim Kr=C4=8Dm=C3=A1=C5=99