From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2081AFEFB4D for ; Fri, 27 Feb 2026 12:57:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7229910EB33; Fri, 27 Feb 2026 12:57:27 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=bootlin.com header.i=@bootlin.com header.b="X7EQanc3"; dkim-atps=neutral Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4A0E910EB33 for ; Fri, 27 Feb 2026 12:57:26 +0000 (UTC) Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 371761A1B89; Fri, 27 Feb 2026 12:57:24 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 0B4025FE46; Fri, 27 Feb 2026 12:57:24 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 1B86C10369428; Fri, 27 Feb 2026 13:57:18 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772197043; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=p+p0UUl562gyk3UrWxUblhbV8MmFN1GLY4UQgsyp6dk=; b=X7EQanc31Nk6ZDDCLs9MR0GMGEiYvqT7ODRxnq+FizLlEVOoVnKGze2osGI77Ae5xYgzIy sCDrRFZKwPs9kXCzb1HqKRU8fKELZb18LPrq1WciEHozVyRcM1MozRNx/QGMdcwrI6WU9S FwqycVZBR4aX9JxsyTf+d0SWj1qE+94Av6NVNlEl0ZeD4ThEHLter31QQbdZXPiRSGQozm fA3+S3qV7MMs1qRsg1dzDb89D5QGpP9bCWoFqKQwMnbJxkpQbIllgmw/OkRSb4XmI1Y7iA UAHiIyr5xVw1bMKkZILteFIrQnPXQmxQvBBaXD0srhw0s3w/A25Sa8pvcfCPbQ== Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 27 Feb 2026 13:57:17 +0100 Message-Id: Cc: "Thomas Petazzoni" , , To: "Luca Ceresoli" , "Andrzej Hajda" , "Neil Armstrong" , "Robert Foss" , "Laurent Pinchart" , "Jonas Karlman" , "Jernej Skrabec" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "David Airlie" , "Simona Vetter" , "Frieder Schrempf" , "Marek Vasut" , "Linus Walleij" From: "Luca Ceresoli" Subject: Re: [PATCH 3/3] drm/bridge: ti-sn65dsi83: add test pattern generation support X-Mailer: aerc 0.20.1 References: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-0-2e15f5a9a6a0@bootlin.com> <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-3-2e15f5a9a6a0@bootlin.com> In-Reply-To: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-3-2e15f5a9a6a0@bootlin.com> X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hello, On Thu Feb 26, 2026 at 5:16 PM CET, Luca Ceresoli wrote: > Generation of a test pattern output is a useful tool for panel bringup an= d > debugging, and very simple to support with this chip. > > The value of REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW needs to be divided by tw= o > for the test pattern to work in dual LVDS mode. While not clearly stated = in > the datasheet, this is needed according to the DSI Tuner [0] output. And > some dual-LVDS panels refuse to show any picture without this division by > two. > > [0] https://www.ti.com/tool/DSI-TUNER > > Signed-off-by: Luca Ceresoli I just noticed a small glitch in the implementation. > +static bool sn65dsi83_test_pattern; > +module_param_named(test_pattern, sn65dsi83_test_pattern, bool, 0644); > + > enum sn65dsi83_channel { > CHANNEL_A, > CHANNEL_B > @@ -645,7 +649,11 @@ static void sn65dsi83_atomic_pre_enable(struct drm_b= ridge *bridge, > REG_LVDS_LANE_CHB_LVDS_TERM : 0)); > regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); > > - le16val =3D cpu_to_le16(mode->hdisplay); > + /* > + * Active line length needs to be halved for test pattern > + * generation in dual LVDS output. > + */ > + le16val =3D cpu_to_le16(mode->hdisplay / (sn65dsi83_test_pattern ? 2 : = 1)); In case sn65dsi83_test_pattern is changed from user space after this cpu_to_le16()... > regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, > &le16val, 2); > le16val =3D cpu_to_le16(mode->vdisplay); > @@ -668,7 +676,8 @@ static void sn65dsi83_atomic_pre_enable(struct drm_br= idge *bridge, > (mode->hsync_start - mode->hdisplay) / dual_factor); > regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, > mode->vsync_start - mode->vdisplay); > - regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); > + regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, > + sn65dsi83_test_pattern ? REG_VID_CHA_TEST_PATTERN_EN : 0); ...but before this regmap_write(), the two registers affected by sn65dsi83_test_pattern would be written with inconsistent values. I'm resending with that fixed. Luca -- Luca Ceresoli, Bootlin Embedded Linux and Kernel engineering https://bootlin.com