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charset=UTF-8 Date: Tue, 10 Mar 2026 19:53:07 +0900 Message-Id: Cc: "Danilo Krummrich" , "Joel Fernandes" , "Timur Tabi" , "Alistair Popple" , "Eliot Courtney" , "Shashank Sharma" , "Zhi Wang" , "David Airlie" , "Simona Vetter" , "Bjorn Helgaas" , "Miguel Ojeda" , "Alex Gaynor" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , , "LKML" Subject: Re: [PATCH v6 21/34] gpu: nova-core: add MCTP/NVDM protocol types for firmware communication From: "Alexandre Courbot" To: "John Hubbard" References: <20260310021125.117855-1-jhubbard@nvidia.com> <20260310021125.117855-22-jhubbard@nvidia.com> In-Reply-To: <20260310021125.117855-22-jhubbard@nvidia.com> X-ClientProxiedBy: TYCP286CA0198.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:385::13) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DS0PR12MB999080:EE_ X-MS-Office365-Filtering-Correlation-Id: ef8e3819-2349-47da-1bc5-08de7e9338b9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|366016|10070799003; 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Both the FSP boot path and the upcoming > GSP RPC message queue share this protocol layer. > > Cc: Joel Fernandes > Signed-off-by: John Hubbard > --- > drivers/gpu/nova-core/mctp.rs | 107 +++++++++++++++++++++++++++++ > drivers/gpu/nova-core/nova_core.rs | 1 + > 2 files changed, 108 insertions(+) > create mode 100644 drivers/gpu/nova-core/mctp.rs > > diff --git a/drivers/gpu/nova-core/mctp.rs b/drivers/gpu/nova-core/mctp.r= s > new file mode 100644 > index 000000000000..0dafc31b230c > --- /dev/null > +++ b/drivers/gpu/nova-core/mctp.rs > @@ -0,0 +1,107 @@ > +// SPDX-License-Identifier: GPL-2.0 > + > +//! MCTP/NVDM protocol types for NVIDIA GPU firmware communication. > +//! > +//! MCTP (Management Component Transport Protocol) carries NVDM (NVIDIA > +//! Device Management) messages between the kernel driver and GPU firmwa= re > +//! processors such as FSP and GSP. > + > +#![expect(dead_code)] > + > +/// NVDM message type identifiers carried over MCTP. > +#[derive(Debug, Clone, Copy, PartialEq, Eq)] > +#[repr(u32)] > +pub(crate) enum NvdmType { > + /// Chain of Trust boot message. > + Cot =3D 0x14, > + /// FSP command response. > + FspResponse =3D 0x15, > +} > + > +/// MCTP transport header for NVIDIA firmware messages. > +/// > +/// Bit layout: `[31] SOM | [30] EOM | [29:28] SEQ | [23:16] SEID`. > +#[derive(Debug, Clone, Copy)] > +pub(crate) struct MctpHeader(u32); > + > +impl MctpHeader { > + const SOM_SHIFT: u32 =3D 31; > + const EOM_SHIFT: u32 =3D 30; > + > + /// Build a single-packet MCTP header (SOM=3D1, EOM=3D1, SEQ=3D0, SE= ID=3D0). > + pub(crate) const fn single_packet() -> Self { > + Self((1 << Self::SOM_SHIFT) | (1 << Self::EOM_SHIFT)) > + } > + > + /// Return the raw packed u32. > + pub(crate) const fn raw(self) -> u32 { > + self.0 > + } > + > + /// Check if this is a complete single-packet message (SOM=3D1 and E= OM=3D1). > + pub(crate) const fn is_single_packet(self) -> bool { > + let som =3D (self.0 >> Self::SOM_SHIFT) & 1; > + let eom =3D (self.0 >> Self::EOM_SHIFT) & 1; > + som =3D=3D 1 && eom =3D=3D 1 > + } > +} > + > +impl From for MctpHeader { > + fn from(raw: u32) -> Self { > + Self(raw) > + } > +} > + > +/// MCTP message type for PCI vendor-defined messages. > +const MSG_TYPE_VENDOR_PCI: u32 =3D 0x7e; > + > +/// NVIDIA PCI vendor ID. > +const VENDOR_ID_NV: u32 =3D 0x10de; > + > +/// NVIDIA Vendor-Defined Message (NVDM) header over MCTP. > +/// > +/// Bit layout: `[6:0] msg_type | [23:8] vendor_id | [31:24] nvdm_type`. > +#[derive(Debug, Clone, Copy)] > +pub(crate) struct NvdmHeader(u32); > + > +impl NvdmHeader { > + const MSG_TYPE_MASK: u32 =3D 0x7f; > + const VENDOR_ID_SHIFT: u32 =3D 8; > + const VENDOR_ID_MASK: u32 =3D 0xffff; > + const TYPE_SHIFT: u32 =3D 24; > + const TYPE_MASK: u32 =3D 0xff; > + > + /// Build an NVDM header for the given message type. > + pub(crate) const fn new(nvdm_type: NvdmType) -> Self { > + Self( > + MSG_TYPE_VENDOR_PCI > + | (VENDOR_ID_NV << Self::VENDOR_ID_SHIFT) > + | ((nvdm_type as u32) << Self::TYPE_SHIFT), > + ) > + } > + > + /// Return the raw packed u32. > + pub(crate) const fn raw(self) -> u32 { > + self.0 > + } > + > + /// Extract the NVDM type field as a raw value. > + pub(crate) const fn nvdm_type_raw(self) -> u32 { > + (self.0 >> Self::TYPE_SHIFT) & Self::TYPE_MASK > + } > + > + /// Validate this header against the expected NVIDIA NVDM format and= type. > + pub(crate) const fn validate(self, expected_type: NvdmType) -> bool = { > + let msg_type =3D self.0 & Self::MSG_TYPE_MASK; > + let vendor_id =3D (self.0 >> Self::VENDOR_ID_SHIFT) & Self::VEND= OR_ID_MASK; > + msg_type =3D=3D MSG_TYPE_VENDOR_PCI > + && vendor_id =3D=3D VENDOR_ID_NV > + && self.nvdm_type_raw() =3D=3D expected_type as u32 > + } > +} > + > +impl From for NvdmHeader { > + fn from(raw: u32) -> Self { > + Self(raw) > + } > +} I think you will want to use the bitfield macro in nova-core/bitfield.rs to define `MctpHeader` and `NvdmHeader` as that's precisely what it is designed to handle. It works like the register macro, without the I/O part.