From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mout-p-102.mailbox.org (mout-p-102.mailbox.org [80.241.56.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A77A37997A; Thu, 16 Apr 2026 05:59:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.152 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776319164; cv=none; b=B4D2Oi9GMNlD0wwRZqWAAVLEQogOaYRd9i2dmCa+2FcvNw0rh6EzPbPopYIWpMv2vw2tyaEUm2C2oYneCcPQK90iPZUBR43Y+gV6IJr6+OFbDsjObAMziVq2SysgB/BaclIB4jzXiQnbsWdWoDl1YzAFz6twmVBr7qqQ8ZqwdwM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776319164; c=relaxed/simple; bh=b6GXcjHcPMiBaPIn941JJJDw3UCq6GnTG0tuVxP2agU=; h=Mime-Version:Content-Type:Date:Message-Id:Subject:From:To:Cc: References:In-Reply-To; b=NfSmw3BqExVMiM9X8yHIC8fALDv1BE6HDTLqf3u1eeyfvi5Em2Be7tx9UIH1wYLbL1lRJPFn0PFEcAJohDIcv/iEwzNeeMxRF/2MGrFNCkd162x0OTXgW3RRoLobElzjiS5VbN+AK6P65fgjGobLbTP8E6KPOZAEqXmfpg0HfnQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=T0d5FZuI; arc=none smtp.client-ip=80.241.56.152 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="T0d5FZuI" Received: from smtp2.mailbox.org (smtp2.mailbox.org [IPv6:2001:67c:2050:b231:465::2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-102.mailbox.org (Postfix) with ESMTPS id 4fx6lq0M0Fz9v9H; Thu, 16 Apr 2026 07:59:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1776319159; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vdYYj6riYPTbHMM03d5MjNlO26UgiwN7VzvRSyjNM9s=; b=T0d5FZuIdovLQSma1yRC/MqVlnad0m/7B26hJJkNPWxROCk60QRoLX6Bc9CAlxB6n2IYfx MvijupiQs9VPfrqOWiy/4JJhd4VBKXd6PyCdV7QuOJk/AG9lfupfKGTQkKXucNabXkIa5a iwQWpZtPhnFoA6mKpS8xtGvZAD2KqMoojSTeo004xk4h8n1YlmMoaMTqEgUQhQtpk9x/w8 IC1iG90Z3MfzFqTuPpc1bi8s9eMMcHAAjfhC4GTi4LwF5ufeMsigGPzMmtbuDsxyrlbbwL 9YHRPd/atHZVjcZNxXj3DcpynbBjF4e2icTPz0tK1MnGVp9jW44Hgezo9OpmxQ== Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 16 Apr 2026 13:59:05 +0800 Message-Id: Subject: Re: [PATCH v2 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC From: "Shuwei Wu" To: "Anand Moon" Cc: "Rafael J. Wysocki" , "Viresh Kumar" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Alexandre Ghiti" , "Yixun Lan" , , , , , References: <20260410-shadow-deps-v2-0-4e16b8c0f60e@mailbox.org> <20260410-shadow-deps-v2-2-4e16b8c0f60e@mailbox.org> In-Reply-To: X-MBO-RS-ID: b7b74779982dba8ead6 X-MBO-RS-META: toouq7rwxsurys33hpqzupw7oknyhwcj On Tue Apr 14, 2026 at 9:25 PM CST, Anand Moon wrote: > Hi Shuwei, > > On Fri, 10 Apr 2026 at 13:30, Shuwei Wu wrote: >> >> Add Operating Performance Points (OPP) tables and CPU clock properties >> for the two clusters in the SpacemiT K1 SoC. >> >> Also assign the CPU power supply (cpu-supply) for the Banana Pi BPI-F3 >> board to fully enable CPU DVFS. >> >> Signed-off-by: Shuwei Wu >> >> --- >> Changes in v2: >> - Add k1-opp.dtsi with OPP tables for both CPU clusters >> - Assign CPU supplies and include OPP table for Banana Pi BPI-F3 >> --- >> arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 35 +++++++- >> arch/riscv/boot/dts/spacemit/k1-opp.dtsi | 105 +++++++++++++++++= +++++++ >> arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++ >> 3 files changed, 147 insertions(+), 1 deletion(-) >> >> diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/risc= v/boot/dts/spacemit/k1-bananapi-f3.dts >> index 444c3b1e6f44..3780593f610d 100644 >> --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts >> +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts >> @@ -5,6 +5,7 @@ >> >> #include "k1.dtsi" >> #include "k1-pinctrl.dtsi" >> +#include "k1-opp.dtsi" >> >> / { >> model =3D "Banana Pi BPI-F3"; >> @@ -86,6 +87,38 @@ &combo_phy { >> status =3D "okay"; >> }; >> >> +&cpu_0 { >> + cpu-supply =3D <&buck1_3v45>; >> +}; >> + >> +&cpu_1 { >> + cpu-supply =3D <&buck1_3v45>; >> +}; >> + >> +&cpu_2 { >> + cpu-supply =3D <&buck1_3v45>; >> +}; >> + >> +&cpu_3 { >> + cpu-supply =3D <&buck1_3v45>; >> +}; >> + >> +&cpu_4 { >> + cpu-supply =3D <&buck1_3v45>; >> +}; >> + >> +&cpu_5 { >> + cpu-supply =3D <&buck1_3v45>; >> +}; >> + >> +&cpu_6 { >> + cpu-supply =3D <&buck1_3v45>; >> +}; >> + >> +&cpu_7 { >> + cpu-supply =3D <&buck1_3v45>; >> +}; >> + >> &emmc { >> bus-width =3D <8>; >> mmc-hs400-1_8v; >> @@ -201,7 +234,7 @@ pmic@41 { >> dldoin2-supply =3D <&buck5>; >> >> regulators { >> - buck1 { >> + buck1_3v45: buck1 { >> regulator-min-microvolt =3D <500000>; >> regulator-max-microvolt =3D <3450000>; >> regulator-ramp-delay =3D <5000>; >> diff --git a/arch/riscv/boot/dts/spacemit/k1-opp.dtsi b/arch/riscv/boot/= dts/spacemit/k1-opp.dtsi >> new file mode 100644 >> index 000000000000..768ae390686d >> --- /dev/null >> +++ b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi >> @@ -0,0 +1,105 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> + >> +/ { >> + cluster0_opp_table: opp-table-cluster0 { >> + compatible =3D "operating-points-v2"; >> + opp-shared; >> + >> + opp-614400000 { >> + opp-hz =3D /bits/ 64 <614400000>; >> + opp-microvolt =3D <950000>; >> + clock-latency-ns =3D <200000>; >> + }; >> + >> + opp-819000000 { >> + opp-hz =3D /bits/ 64 <819000000>; >> + opp-microvolt =3D <950000>; >> + clock-latency-ns =3D <200000>; >> + }; >> + >> + opp-1000000000 { >> + opp-hz =3D /bits/ 64 <1000000000>; >> + opp-microvolt =3D <950000>; >> + clock-latency-ns =3D <200000>; >> + }; >> + >> + opp-1228800000 { >> + opp-hz =3D /bits/ 64 <1228800000>; >> + opp-microvolt =3D <950000>; >> + clock-latency-ns =3D <200000>; >> + }; >> + >> + opp-1600000000 { >> + opp-hz =3D /bits/ 64 <1600000000>; >> + opp-microvolt =3D <1050000>; >> + clock-latency-ns =3D <200000>; >> + }; >> + }; >> + >> + cluster1_opp_table: opp-table-cluster1 { >> + compatible =3D "operating-points-v2"; >> + opp-shared; >> + >> + opp-614400000 { >> + opp-hz =3D /bits/ 64 <614400000>; >> + opp-microvolt =3D <950000>; >> + clock-latency-ns =3D <200000>; >> + }; >> + >> + opp-819000000 { >> + opp-hz =3D /bits/ 64 <819000000>; >> + opp-microvolt =3D <950000>; >> + clock-latency-ns =3D <200000>; >> + }; >> + >> + opp-1000000000 { >> + opp-hz =3D /bits/ 64 <1000000000>; >> + opp-microvolt =3D <950000>; >> + clock-latency-ns =3D <200000>; >> + }; >> + >> + opp-1228800000 { >> + opp-hz =3D /bits/ 64 <1228800000>; >> + opp-microvolt =3D <950000>; >> + clock-latency-ns =3D <200000>; >> + }; >> + >> + opp-1600000000 { >> + opp-hz =3D /bits/ 64 <1600000000>; >> + opp-microvolt =3D <1050000>; >> + clock-latency-ns =3D <200000>; >> + }; >> + }; >> +}; >> + >> +&cpu_0 { >> + operating-points-v2 =3D <&cluster0_opp_table>; >> +}; >> + >> +&cpu_1 { >> + operating-points-v2 =3D <&cluster0_opp_table>; >> +}; >> + >> +&cpu_2 { >> + operating-points-v2 =3D <&cluster0_opp_table>; >> +}; >> + >> +&cpu_3 { >> + operating-points-v2 =3D <&cluster0_opp_table>; >> +}; >> + >> +&cpu_4 { >> + operating-points-v2 =3D <&cluster1_opp_table>; >> +}; >> + >> +&cpu_5 { >> + operating-points-v2 =3D <&cluster1_opp_table>; >> +}; >> + >> +&cpu_6 { >> + operating-points-v2 =3D <&cluster1_opp_table>; >> +}; >> + >> +&cpu_7 { >> + operating-points-v2 =3D <&cluster1_opp_table>; >> +}; >> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/= spacemit/k1.dtsi >> index 529ec68e9c23..bdd109b81730 100644 >> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi >> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi >> @@ -54,6 +54,7 @@ cpu_0: cpu@0 { >> compatible =3D "spacemit,x60", "riscv"; >> device_type =3D "cpu"; >> reg =3D <0>; >> + clocks =3D <&syscon_apmu CLK_CPU_C0_CORE>; >> riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz= _zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvf= h_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; >> riscv,isa-base =3D "rv64i"; >> riscv,isa-extensions =3D "i", "m", "a", "f", "d"= , "c", "b", "v", "zicbom", >> @@ -84,6 +85,7 @@ cpu_1: cpu@1 { >> compatible =3D "spacemit,x60", "riscv"; >> device_type =3D "cpu"; >> reg =3D <1>; >> + clocks =3D <&syscon_apmu CLK_CPU_C0_CORE>; > > Based on the Spacemit kernel source, the k1-x_opp_table.dtsi file > defines several additional clocks for the Operating Performance Points > (OPP) table: > > clocks =3D <&ccu CLK_CPU_C0_ACE>, <&ccu CLK_CPU_C1_ACE>, <&ccu CLK_CPU_C= 0_TCM>, > <&ccu CLK_CCI550>, <&ccu CLK_PLL3>, <&ccu > CLK_CPU_C0_HI>, <&ccu CLK_CPU_C1_HI>; > clock-names =3D "ace0","ace1","tcm","cci","pll3", "c0hi",= "c1hi"; > > These hardware clocks are also explicitly registered in the APMU clock dr= iver > via the k1_ccu_apmu_hws array, confirming their availability for frequenc= y > and voltage scaling on the K1-X SoC. > > static struct clk_hw *k1_ccu_apmu_hws[] =3D { > [CLK_CCI550] =3D &cci550_clk.common.hw, > [CLK_CPU_C0_HI] =3D &cpu_c0_hi_clk.common.hw, > [CLK_CPU_C0_CORE] =3D &cpu_c0_core_clk.common.hw, > [CLK_CPU_C0_ACE] =3D &cpu_c0_ace_clk.common.hw, > [CLK_CPU_C0_TCM] =3D &cpu_c0_tcm_clk.common.hw, > [CLK_CPU_C1_HI] =3D &cpu_c1_hi_clk.common.hw, > [CLK_CPU_C1_CORE] =3D &cpu_c1_core_clk.common.hw, > [CLK_CPU_C1_ACE] =3D &cpu_c1_ace_clk.common.hw, > > Yes, it is possible to add these clocks for DVFS to work correctly, > provided they are managed by the appropriate driver and declared in > the Device Tree (DT). > > Thanks > -Anand Thanks for your review and for pointing this out. Regarding the clocks you mentioned, I'd like to clarify their roles based o= n the K1 datasheet. Taking Cluster 0 as an example, c0_core_clk is the primar= y clock for the cluster. c0_ace_clk and c0_tcm_clk are children derived from = it, defaulting to half the frequency of their parent core clock, while c0_hi_cl= k represents the high-speed path selection. Cluster 1 follows the same structure. Based on the official SpacemiT Bianbu OS source, the spacemit-cpufreq.c dri= ver mainly performs the following tasks: 1. Sets the CCI550 clock frequency to 614MHz. 2. Sets the clock frequencies of c0_ace_clk, c1_ace1_clk, and c0_tcm_clk to= half the frequency of their parent clock. 3. For the 1.6GHz OPP, it sets the PLL3 frequency to 3.2GHz and the c0_hi_clk/c1_hi_clk frequencies to 1.6GHz. I booted with the manufacturer's OpenWRT image and used debugfs to confirm = that the clock states are exactly as described above. At 1.6GHz: Clock Source & Tree Rate (Hz) HW Enable Consumer --------------------------------------------------------------------------- pll3 3,200,000,000 Y deviceless =E2=94=94=E2=94=80 pll3_d2 1,600,000,000 Y dev= iceless =E2=94=9C=E2=94=80 cpu_c1_hi_clk 1,600,000,000 Y dev= iceless =E2=94=82 =E2=94=94=E2=94=80 cpu_c1_pclk 1,600,000,000 Y = cpu0 =E2=94=82 =E2=94=94=E2=94=80 cpu_c1_ace_clk 800,000,000 Y = deviceless =E2=94=94=E2=94=80 cpu_c0_hi_clk 1,600,000,000 Y dev= iceless =E2=94=94=E2=94=80 cpu_c0_core_clk 1,600,000,000 Y cpu= 0 =E2=94=9C=E2=94=80 cpu_c0_tcm_clk 800,000,000 Y dev= iceless =E2=94=94=E2=94=80 cpu_c0_ace_clk 800,000,000 Y dev= iceless pll1_2457p6_vco 2,457,600,000 Y deviceless =E2=94=94=E2=94=80 pll1_d4 614,400,000 Y dev= iceless =E2=94=94=E2=94=80 pll1_d4_614p4 614,400,000 Y dev= iceless =E2=94=94=E2=94=80 cci550_clk 614,400,000 Y dev= iceless At 1.228GHz: Clock Source & Tree Rate (Hz) HW Enable Consumer --------------------------------------------------------------------------- pll1_2457p6_vco 2,457,600,000 Y deviceless =E2=94=94=E2=94=80 pll1_d2 1,228,800,000 Y dev= iceless =E2=94=94=E2=94=80 pll1_d2_1228p8 1,228,800,000 Y dev= iceless =E2=94=9C=E2=94=80 cpu_c0_core_clk 1,228,800,000 Y cpu= 0 =E2=94=82 =E2=94=9C=E2=94=80 cpu_c0_tcm_clk 614,400,000 Y = deviceless =E2=94=82 =E2=94=94=E2=94=80 cpu_c0_ace_clk 614,400,000 Y = deviceless =E2=94=94=E2=94=80 cpu_c1_pclk 1,228,800,000 Y cpu= 0 =E2=94=94=E2=94=80 cpu_c1_ace_clk 614,400,000 Y dev= iceless =E2=94=94=E2=94=80 pll1_d4 614,400,000 Y de= viceless =E2=94=94=E2=94=80 pll1_d4_614p4 614,400,000 Y dev= iceless =E2=94=94=E2=94=80 cci550_clk 614,400,000 Y dev= iceless pll3 3,200,000,000 Y deviceless =E2=94=94=E2=94=80 pll3_d2 1,600,000,000 Y dev= iceless =E2=94=9C=E2=94=80 cpu_c1_hi_clk 1,600,000,000 Y dev= iceless =E2=94=94=E2=94=80 cpu_c0_hi_clk 1,600,000,000 Y dev= iceless =E2=94=94=E2=94=80 pll3_d3 1,066,666,666 Y dev= iceless Regarding the necessity of listing these clocks in the DT, my analysis is a= s follows: 1. For CCI550, I did not find a clear definition of this clock's specific r= ole in the SoC datasheet. Although the vendor kernel increases its frequency, my benchmarks show that maintaining the mainline default (245.76MHz) has a negligible impact on CPU performance. 2. For ACE and TCM clocks, they function as synchronous children of the cor= e clock with a default divide-by-2 ratio. Since they scale automatically rela= tive to c0_core_clk/c1_core_clk and no other peripherals depend on them, they do= not require manual management in the OPP table. 3. For the high-speed path, the underlying clock controller logic already h= andles the parent MUX switching and PLL3 scaling automatically when clk_set_rate() is called on the core clock. I have verified this by checking the hardware state in the mainline kernel. The clock tree matches the vendor kernel's configuration: At 1.6GHz: Clock Source & Tree Rate (Hz) HW Enable Consumer --------------------------------------------------------------------------- pll3 3,200,000,000 Y deviceless =E2=94=94=E2=94=80 pll3_d2 1,600,000,000 Y dev= iceless =E2=94=9C=E2=94=80 cpu_c1_hi_clk 1,600,000,000 Y dev= iceless =E2=94=82 =E2=94=94=E2=94=80 cpu_c1_core_clk 1,600,000,000 Y = cpu4 =E2=94=82 =E2=94=94=E2=94=80 cpu_c1_ace_clk 800,000,000 Y = deviceless =E2=94=94=E2=94=80 cpu_c0_hi_clk 1,600,000,000 Y dev= iceless =E2=94=94=E2=94=80 cpu_c0_core_clk 1,600,000,000 Y cpu= 0 =E2=94=9C=E2=94=80 cpu_c0_tcm_clk 800,000,000 Y dev= iceless =E2=94=94=E2=94=80 cpu_c0_ace_clk 800,000,000 Y dev= iceless pll1 2,457,600,000 Y deviceless =E2=94=94=E2=94=80 pll1_d5 491,520,000 Y dev= iceless =E2=94=94=E2=94=80 pll1_d5_491p52 491,520,000 Y dev= iceless =E2=94=94=E2=94=80 cci550_clk 245,760,000 Y dev= iceless At 1.228GHz: Clock Source & Tree Rate (Hz) HW Enable Consumer --------------------------------------------------------------------------- pll1 2,457,600,000 Y deviceless =E2=94=9C=E2=94=80 pll1_d5 491,520,000 Y dev= iceless =E2=94=82 =E2=94=94=E2=94=80 pll1_d5_491p52 491,520,000 Y = deviceless =E2=94=82 =E2=94=94=E2=94=80 cci550_clk 245,760,000 Y = deviceless =E2=94=94=E2=94=80 pll1_d2 1,228,800,000 Y dev= iceless =E2=94=94=E2=94=80 pll1_d2_1228p8 1,228,800,000 Y dev= iceless =E2=94=94=E2=94=80 cpu_c0_core_clk 1,228,800,000 Y cpu= 0 =E2=94=9C=E2=94=80 cpu_c0_tcm_clk 614,400,000 Y dev= iceless =E2=94=94=E2=94=80 cpu_c0_ace_clk 614,400,000 Y dev= iceless pll3 3,200,000,000 Y deviceless =E2=94=94=E2=94=80 pll3_d2 1,600,000,000 Y dev= iceless =E2=94=94=E2=94=80 cpu_c1_hi_clk 1,600,000,000 Y dev= iceless =E2=94=94=E2=94=80 cpu_c1_core_clk 1,600,000,000 Y cpu= 4 =E2=94=94=E2=94=80 cpu_c1_ace_clk 800,000,000 Y dev= iceless Performance benchmarks also confirm that the current configuration is suffi= cient: Benchmark (AWK computation): time awk 'BEGIN{for(i=3D0;i<10000000;i++) sum+= =3Di}' ---------------------------------------------------------------------------= - Frequency | Mainline Linux (s) | OpenWrt (s) = =20 (kHz) | Real (Total) | User (CPU) | Real (Total) | User (CPU) = ) -------------+---------------+---------------+---------------+-------------= - 1,600,000 | 1.82s | 1.81s | 1.73s | 1.73s = =20 1,228,800 | 2.34s | 2.33s | 2.26s | 2.26s = =20 1,000,000 | 2.94s | 2.86s | 2.78s | 2.78s = =20 819,000 | 3.54s | 3.53s | 3.39s | 3.39s = =20 614,400 | 4.73s | 4.71s | 4.51s | 4.51s = =20 ---------------------------------------------------------------------------= - In summary, because the clock controller correctly handles the internal div= iders and parent switching, declaring only the primary core clock for each CPU no= de is sufficient for functional DVFS. --=20 Best regards, Shuwei Wu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C035F433FE for ; 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b=T0d5FZuIdovLQSma1yRC/MqVlnad0m/7B26hJJkNPWxROCk60QRoLX6Bc9CAlxB6n2IYfx MvijupiQs9VPfrqOWiy/4JJhd4VBKXd6PyCdV7QuOJk/AG9lfupfKGTQkKXucNabXkIa5a iwQWpZtPhnFoA6mKpS8xtGvZAD2KqMoojSTeo004xk4h8n1YlmMoaMTqEgUQhQtpk9x/w8 IC1iG90Z3MfzFqTuPpc1bi8s9eMMcHAAjfhC4GTi4LwF5ufeMsigGPzMmtbuDsxyrlbbwL 9YHRPd/atHZVjcZNxXj3DcpynbBjF4e2icTPz0tK1MnGVp9jW44Hgezo9OpmxQ== Mime-Version: 1.0 Date: Thu, 16 Apr 2026 13:59:05 +0800 Message-Id: Subject: Re: [PATCH v2 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC From: "Shuwei Wu" To: "Anand Moon" Cc: "Rafael J. Wysocki" , "Viresh Kumar" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Alexandre Ghiti" , "Yixun Lan" , , , , , References: <20260410-shadow-deps-v2-0-4e16b8c0f60e@mailbox.org> <20260410-shadow-deps-v2-2-4e16b8c0f60e@mailbox.org> In-Reply-To: X-MBO-RS-ID: b7b74779982dba8ead6 X-MBO-RS-META: toouq7rwxsurys33hpqzupw7oknyhwcj X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260415_225925_805151_D491A0A6 X-CRM114-Status: GOOD ( 23.74 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gVHVlIEFwciAxNCwgMjAyNiBhdCA5OjI1IFBNIENTVCwgQW5hbmQgTW9vbiB3cm90ZToKPiBI aSBTaHV3ZWksCj4KPiBPbiBGcmksIDEwIEFwciAyMDI2IGF0IDEzOjMwLCBTaHV3ZWkgV3UgPHNo dXdlaS53dUBtYWlsYm94Lm9yZz4gd3JvdGU6Cj4+Cj4+IEFkZCBPcGVyYXRpbmcgUGVyZm9ybWFu Y2UgUG9pbnRzIChPUFApIHRhYmxlcyBhbmQgQ1BVIGNsb2NrIHByb3BlcnRpZXMKPj4gZm9yIHRo ZSB0d28gY2x1c3RlcnMgaW4gdGhlIFNwYWNlbWlUIEsxIFNvQy4KPj4KPj4gQWxzbyBhc3NpZ24g dGhlIENQVSBwb3dlciBzdXBwbHkgKGNwdS1zdXBwbHkpIGZvciB0aGUgQmFuYW5hIFBpIEJQSS1G Mwo+PiBib2FyZCB0byBmdWxseSBlbmFibGUgQ1BVIERWRlMuCj4+Cj4+IFNpZ25lZC1vZmYtYnk6 IFNodXdlaSBXdSA8c2h1d2VpLnd1QG1haWxib3gub3JnPgo+Pgo+PiAtLS0KPj4gQ2hhbmdlcyBp biB2MjoKPj4gLSBBZGQgazEtb3BwLmR0c2kgd2l0aCBPUFAgdGFibGVzIGZvciBib3RoIENQVSBj bHVzdGVycwo+PiAtIEFzc2lnbiBDUFUgc3VwcGxpZXMgYW5kIGluY2x1ZGUgT1BQIHRhYmxlIGZv ciBCYW5hbmEgUGkgQlBJLUYzCj4+IC0tLQo+PiAgYXJjaC9yaXNjdi9ib290L2R0cy9zcGFjZW1p dC9rMS1iYW5hbmFwaS1mMy5kdHMgfCAgMzUgKysrKysrKy0KPj4gIGFyY2gvcmlzY3YvYm9vdC9k dHMvc3BhY2VtaXQvazEtb3BwLmR0c2kgICAgICAgIHwgMTA1ICsrKysrKysrKysrKysrKysrKysr KysrKwo+PiAgYXJjaC9yaXNjdi9ib290L2R0cy9zcGFjZW1pdC9rMS5kdHNpICAgICAgICAgICAg fCAgIDggKysKPj4gIDMgZmlsZXMgY2hhbmdlZCwgMTQ3IGluc2VydGlvbnMoKyksIDEgZGVsZXRp b24oLSkKPj4KPj4gZGlmZiAtLWdpdCBhL2FyY2gvcmlzY3YvYm9vdC9kdHMvc3BhY2VtaXQvazEt YmFuYW5hcGktZjMuZHRzIGIvYXJjaC9yaXNjdi9ib290L2R0cy9zcGFjZW1pdC9rMS1iYW5hbmFw aS1mMy5kdHMKPj4gaW5kZXggNDQ0YzNiMWU2ZjQ0Li4zNzgwNTkzZjYxMGQgMTAwNjQ0Cj4+IC0t LSBhL2FyY2gvcmlzY3YvYm9vdC9kdHMvc3BhY2VtaXQvazEtYmFuYW5hcGktZjMuZHRzCj4+ICsr KyBiL2FyY2gvcmlzY3YvYm9vdC9kdHMvc3BhY2VtaXQvazEtYmFuYW5hcGktZjMuZHRzCj4+IEBA IC01LDYgKzUsNyBAQAo+Pgo+PiAgI2luY2x1ZGUgImsxLmR0c2kiCj4+ICAjaW5jbHVkZSAiazEt cGluY3RybC5kdHNpIgo+PiArI2luY2x1ZGUgImsxLW9wcC5kdHNpIgo+Pgo+PiAgLyB7Cj4+ICAg ICAgICAgbW9kZWwgPSAiQmFuYW5hIFBpIEJQSS1GMyI7Cj4+IEBAIC04Niw2ICs4NywzOCBAQCAm Y29tYm9fcGh5IHsKPj4gICAgICAgICBzdGF0dXMgPSAib2theSI7Cj4+ICB9Owo+Pgo+PiArJmNw dV8wIHsKPj4gKyAgICAgICBjcHUtc3VwcGx5ID0gPCZidWNrMV8zdjQ1PjsKPj4gK307Cj4+ICsK Pj4gKyZjcHVfMSB7Cj4+ICsgICAgICAgY3B1LXN1cHBseSA9IDwmYnVjazFfM3Y0NT47Cj4+ICt9 Owo+PiArCj4+ICsmY3B1XzIgewo+PiArICAgICAgIGNwdS1zdXBwbHkgPSA8JmJ1Y2sxXzN2NDU+ Owo+PiArfTsKPj4gKwo+PiArJmNwdV8zIHsKPj4gKyAgICAgICBjcHUtc3VwcGx5ID0gPCZidWNr MV8zdjQ1PjsKPj4gK307Cj4+ICsKPj4gKyZjcHVfNCB7Cj4+ICsgICAgICAgY3B1LXN1cHBseSA9 IDwmYnVjazFfM3Y0NT47Cj4+ICt9Owo+PiArCj4+ICsmY3B1XzUgewo+PiArICAgICAgIGNwdS1z dXBwbHkgPSA8JmJ1Y2sxXzN2NDU+Owo+PiArfTsKPj4gKwo+PiArJmNwdV82IHsKPj4gKyAgICAg ICBjcHUtc3VwcGx5ID0gPCZidWNrMV8zdjQ1PjsKPj4gK307Cj4+ICsKPj4gKyZjcHVfNyB7Cj4+ ICsgICAgICAgY3B1LXN1cHBseSA9IDwmYnVjazFfM3Y0NT47Cj4+ICt9Owo+PiArCj4+ICAmZW1t YyB7Cj4+ICAgICAgICAgYnVzLXdpZHRoID0gPDg+Owo+PiAgICAgICAgIG1tYy1oczQwMC0xXzh2 Owo+PiBAQCAtMjAxLDcgKzIzNCw3IEBAIHBtaWNANDEgewo+PiAgICAgICAgICAgICAgICAgZGxk b2luMi1zdXBwbHkgPSA8JmJ1Y2s1PjsKPj4KPj4gICAgICAgICAgICAgICAgIHJlZ3VsYXRvcnMg ewo+PiAtICAgICAgICAgICAgICAgICAgICAgICBidWNrMSB7Cj4+ICsgICAgICAgICAgICAgICAg ICAgICAgIGJ1Y2sxXzN2NDU6IGJ1Y2sxIHsKPj4gICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICByZWd1bGF0b3ItbWluLW1pY3Jvdm9sdCA9IDw1MDAwMDA+Owo+PiAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgIHJlZ3VsYXRvci1tYXgtbWljcm92b2x0ID0gPDM0NTAwMDA+Owo+ PiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHJlZ3VsYXRvci1yYW1wLWRlbGF5ID0g PDUwMDA+Owo+PiBkaWZmIC0tZ2l0IGEvYXJjaC9yaXNjdi9ib290L2R0cy9zcGFjZW1pdC9rMS1v cHAuZHRzaSBiL2FyY2gvcmlzY3YvYm9vdC9kdHMvc3BhY2VtaXQvazEtb3BwLmR0c2kKPj4gbmV3 IGZpbGUgbW9kZSAxMDA2NDQKPj4gaW5kZXggMDAwMDAwMDAwMDAwLi43NjhhZTM5MDY4NmQKPj4g LS0tIC9kZXYvbnVsbAo+PiArKysgYi9hcmNoL3Jpc2N2L2Jvb3QvZHRzL3NwYWNlbWl0L2sxLW9w cC5kdHNpCj4+IEBAIC0wLDAgKzEsMTA1IEBACj4+ICsvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmll cjogKEdQTC0yLjArIE9SIE1JVCkKPj4gKwo+PiArLyB7Cj4+ICsgICAgICAgY2x1c3RlcjBfb3Bw X3RhYmxlOiBvcHAtdGFibGUtY2x1c3RlcjAgewo+PiArICAgICAgICAgICAgICAgY29tcGF0aWJs ZSA9ICJvcGVyYXRpbmctcG9pbnRzLXYyIjsKPj4gKyAgICAgICAgICAgICAgIG9wcC1zaGFyZWQ7 Cj4+ICsKPj4gKyAgICAgICAgICAgICAgIG9wcC02MTQ0MDAwMDAgewo+PiArICAgICAgICAgICAg ICAgICAgICAgICBvcHAtaHogPSAvYml0cy8gNjQgPDYxNDQwMDAwMD47Cj4+ICsgICAgICAgICAg ICAgICAgICAgICAgIG9wcC1taWNyb3ZvbHQgPSA8OTUwMDAwPjsKPj4gKyAgICAgICAgICAgICAg ICAgICAgICAgY2xvY2stbGF0ZW5jeS1ucyA9IDwyMDAwMDA+Owo+PiArICAgICAgICAgICAgICAg fTsKPj4gKwo+PiArICAgICAgICAgICAgICAgb3BwLTgxOTAwMDAwMCB7Cj4+ICsgICAgICAgICAg ICAgICAgICAgICAgIG9wcC1oeiA9IC9iaXRzLyA2NCA8ODE5MDAwMDAwPjsKPj4gKyAgICAgICAg ICAgICAgICAgICAgICAgb3BwLW1pY3Jvdm9sdCA9IDw5NTAwMDA+Owo+PiArICAgICAgICAgICAg ICAgICAgICAgICBjbG9jay1sYXRlbmN5LW5zID0gPDIwMDAwMD47Cj4+ICsgICAgICAgICAgICAg ICB9Owo+PiArCj4+ICsgICAgICAgICAgICAgICBvcHAtMTAwMDAwMDAwMCB7Cj4+ICsgICAgICAg ICAgICAgICAgICAgICAgIG9wcC1oeiA9IC9iaXRzLyA2NCA8MTAwMDAwMDAwMD47Cj4+ICsgICAg ICAgICAgICAgICAgICAgICAgIG9wcC1taWNyb3ZvbHQgPSA8OTUwMDAwPjsKPj4gKyAgICAgICAg ICAgICAgICAgICAgICAgY2xvY2stbGF0ZW5jeS1ucyA9IDwyMDAwMDA+Owo+PiArICAgICAgICAg ICAgICAgfTsKPj4gKwo+PiArICAgICAgICAgICAgICAgb3BwLTEyMjg4MDAwMDAgewo+PiArICAg ICAgICAgICAgICAgICAgICAgICBvcHAtaHogPSAvYml0cy8gNjQgPDEyMjg4MDAwMDA+Owo+PiAr ICAgICAgICAgICAgICAgICAgICAgICBvcHAtbWljcm92b2x0ID0gPDk1MDAwMD47Cj4+ICsgICAg ICAgICAgICAgICAgICAgICAgIGNsb2NrLWxhdGVuY3ktbnMgPSA8MjAwMDAwPjsKPj4gKyAgICAg ICAgICAgICAgIH07Cj4+ICsKPj4gKyAgICAgICAgICAgICAgIG9wcC0xNjAwMDAwMDAwIHsKPj4g KyAgICAgICAgICAgICAgICAgICAgICAgb3BwLWh6ID0gL2JpdHMvIDY0IDwxNjAwMDAwMDAwPjsK Pj4gKyAgICAgICAgICAgICAgICAgICAgICAgb3BwLW1pY3Jvdm9sdCA9IDwxMDUwMDAwPjsKPj4g KyAgICAgICAgICAgICAgICAgICAgICAgY2xvY2stbGF0ZW5jeS1ucyA9IDwyMDAwMDA+Owo+PiAr ICAgICAgICAgICAgICAgfTsKPj4gKyAgICAgICB9Owo+PiArCj4+ICsgICAgICAgY2x1c3RlcjFf b3BwX3RhYmxlOiBvcHAtdGFibGUtY2x1c3RlcjEgewo+PiArICAgICAgICAgICAgICAgY29tcGF0 aWJsZSA9ICJvcGVyYXRpbmctcG9pbnRzLXYyIjsKPj4gKyAgICAgICAgICAgICAgIG9wcC1zaGFy ZWQ7Cj4+ICsKPj4gKyAgICAgICAgICAgICAgIG9wcC02MTQ0MDAwMDAgewo+PiArICAgICAgICAg ICAgICAgICAgICAgICBvcHAtaHogPSAvYml0cy8gNjQgPDYxNDQwMDAwMD47Cj4+ICsgICAgICAg ICAgICAgICAgICAgICAgIG9wcC1taWNyb3ZvbHQgPSA8OTUwMDAwPjsKPj4gKyAgICAgICAgICAg ICAgICAgICAgICAgY2xvY2stbGF0ZW5jeS1ucyA9IDwyMDAwMDA+Owo+PiArICAgICAgICAgICAg ICAgfTsKPj4gKwo+PiArICAgICAgICAgICAgICAgb3BwLTgxOTAwMDAwMCB7Cj4+ICsgICAgICAg ICAgICAgICAgICAgICAgIG9wcC1oeiA9IC9iaXRzLyA2NCA8ODE5MDAwMDAwPjsKPj4gKyAgICAg ICAgICAgICAgICAgICAgICAgb3BwLW1pY3Jvdm9sdCA9IDw5NTAwMDA+Owo+PiArICAgICAgICAg ICAgICAgICAgICAgICBjbG9jay1sYXRlbmN5LW5zID0gPDIwMDAwMD47Cj4+ICsgICAgICAgICAg ICAgICB9Owo+PiArCj4+ICsgICAgICAgICAgICAgICBvcHAtMTAwMDAwMDAwMCB7Cj4+ICsgICAg ICAgICAgICAgICAgICAgICAgIG9wcC1oeiA9IC9iaXRzLyA2NCA8MTAwMDAwMDAwMD47Cj4+ICsg ICAgICAgICAgICAgICAgICAgICAgIG9wcC1taWNyb3ZvbHQgPSA8OTUwMDAwPjsKPj4gKyAgICAg ICAgICAgICAgICAgICAgICAgY2xvY2stbGF0ZW5jeS1ucyA9IDwyMDAwMDA+Owo+PiArICAgICAg ICAgICAgICAgfTsKPj4gKwo+PiArICAgICAgICAgICAgICAgb3BwLTEyMjg4MDAwMDAgewo+PiAr ICAgICAgICAgICAgICAgICAgICAgICBvcHAtaHogPSAvYml0cy8gNjQgPDEyMjg4MDAwMDA+Owo+ PiArICAgICAgICAgICAgICAgICAgICAgICBvcHAtbWljcm92b2x0ID0gPDk1MDAwMD47Cj4+ICsg ICAgICAgICAgICAgICAgICAgICAgIGNsb2NrLWxhdGVuY3ktbnMgPSA8MjAwMDAwPjsKPj4gKyAg ICAgICAgICAgICAgIH07Cj4+ICsKPj4gKyAgICAgICAgICAgICAgIG9wcC0xNjAwMDAwMDAwIHsK Pj4gKyAgICAgICAgICAgICAgICAgICAgICAgb3BwLWh6ID0gL2JpdHMvIDY0IDwxNjAwMDAwMDAw PjsKPj4gKyAgICAgICAgICAgICAgICAgICAgICAgb3BwLW1pY3Jvdm9sdCA9IDwxMDUwMDAwPjsK Pj4gKyAgICAgICAgICAgICAgICAgICAgICAgY2xvY2stbGF0ZW5jeS1ucyA9IDwyMDAwMDA+Owo+ PiArICAgICAgICAgICAgICAgfTsKPj4gKyAgICAgICB9Owo+PiArfTsKPj4gKwo+PiArJmNwdV8w IHsKPj4gKyAgICAgICBvcGVyYXRpbmctcG9pbnRzLXYyID0gPCZjbHVzdGVyMF9vcHBfdGFibGU+ Owo+PiArfTsKPj4gKwo+PiArJmNwdV8xIHsKPj4gKyAgICAgICBvcGVyYXRpbmctcG9pbnRzLXYy ID0gPCZjbHVzdGVyMF9vcHBfdGFibGU+Owo+PiArfTsKPj4gKwo+PiArJmNwdV8yIHsKPj4gKyAg ICAgICBvcGVyYXRpbmctcG9pbnRzLXYyID0gPCZjbHVzdGVyMF9vcHBfdGFibGU+Owo+PiArfTsK Pj4gKwo+PiArJmNwdV8zIHsKPj4gKyAgICAgICBvcGVyYXRpbmctcG9pbnRzLXYyID0gPCZjbHVz dGVyMF9vcHBfdGFibGU+Owo+PiArfTsKPj4gKwo+PiArJmNwdV80IHsKPj4gKyAgICAgICBvcGVy YXRpbmctcG9pbnRzLXYyID0gPCZjbHVzdGVyMV9vcHBfdGFibGU+Owo+PiArfTsKPj4gKwo+PiAr JmNwdV81IHsKPj4gKyAgICAgICBvcGVyYXRpbmctcG9pbnRzLXYyID0gPCZjbHVzdGVyMV9vcHBf dGFibGU+Owo+PiArfTsKPj4gKwo+PiArJmNwdV82IHsKPj4gKyAgICAgICBvcGVyYXRpbmctcG9p bnRzLXYyID0gPCZjbHVzdGVyMV9vcHBfdGFibGU+Owo+PiArfTsKPj4gKwo+PiArJmNwdV83IHsK Pj4gKyAgICAgICBvcGVyYXRpbmctcG9pbnRzLXYyID0gPCZjbHVzdGVyMV9vcHBfdGFibGU+Owo+ PiArfTsKPj4gZGlmZiAtLWdpdCBhL2FyY2gvcmlzY3YvYm9vdC9kdHMvc3BhY2VtaXQvazEuZHRz aSBiL2FyY2gvcmlzY3YvYm9vdC9kdHMvc3BhY2VtaXQvazEuZHRzaQo+PiBpbmRleCA1MjllYzY4 ZTljMjMuLmJkZDEwOWI4MTczMCAxMDA2NDQKPj4gLS0tIGEvYXJjaC9yaXNjdi9ib290L2R0cy9z cGFjZW1pdC9rMS5kdHNpCj4+ICsrKyBiL2FyY2gvcmlzY3YvYm9vdC9kdHMvc3BhY2VtaXQvazEu ZHRzaQo+PiBAQCAtNTQsNiArNTQsNyBAQCBjcHVfMDogY3B1QDAgewo+PiAgICAgICAgICAgICAg ICAgICAgICAgICBjb21wYXRpYmxlID0gInNwYWNlbWl0LHg2MCIsICJyaXNjdiI7Cj4+ICAgICAg ICAgICAgICAgICAgICAgICAgIGRldmljZV90eXBlID0gImNwdSI7Cj4+ICAgICAgICAgICAgICAg ICAgICAgICAgIHJlZyA9IDwwPjsKPj4gKyAgICAgICAgICAgICAgICAgICAgICAgY2xvY2tzID0g PCZzeXNjb25fYXBtdSBDTEtfQ1BVX0MwX0NPUkU+Owo+PiAgICAgICAgICAgICAgICAgICAgICAg ICByaXNjdixpc2EgPSAicnY2NGltYWZkY2J2X3ppY2JvbV96aWNib3BfemljYm96X3ppY250cl96 aWNvbmRfemljc3JfemlmZW5jZWlfemloaW50cGF1c2VfemlocG1femZoX3piYV96YmJfemJjX3pi c196a3RfenZmaF96dmt0X3NzY29mcG1mX3NzdGNfc3ZpbnZhbF9zdm5hcG90X3N2cGJtdCI7Cj4+ ICAgICAgICAgICAgICAgICAgICAgICAgIHJpc2N2LGlzYS1iYXNlID0gInJ2NjRpIjsKPj4gICAg ICAgICAgICAgICAgICAgICAgICAgcmlzY3YsaXNhLWV4dGVuc2lvbnMgPSAiaSIsICJtIiwgImEi LCAiZiIsICJkIiwgImMiLCAiYiIsICJ2IiwgInppY2JvbSIsCj4+IEBAIC04NCw2ICs4NSw3IEBA IGNwdV8xOiBjcHVAMSB7Cj4+ICAgICAgICAgICAgICAgICAgICAgICAgIGNvbXBhdGlibGUgPSAi c3BhY2VtaXQseDYwIiwgInJpc2N2IjsKPj4gICAgICAgICAgICAgICAgICAgICAgICAgZGV2aWNl X3R5cGUgPSAiY3B1IjsKPj4gICAgICAgICAgICAgICAgICAgICAgICAgcmVnID0gPDE+Owo+PiAr ICAgICAgICAgICAgICAgICAgICAgICBjbG9ja3MgPSA8JnN5c2Nvbl9hcG11IENMS19DUFVfQzBf Q09SRT47Cj4KPiBCYXNlZCBvbiB0aGUgU3BhY2VtaXQga2VybmVsIHNvdXJjZSwgdGhlIGsxLXhf b3BwX3RhYmxlLmR0c2kgZmlsZQo+IGRlZmluZXMgc2V2ZXJhbCBhZGRpdGlvbmFsIGNsb2NrcyBm b3IgdGhlIE9wZXJhdGluZyBQZXJmb3JtYW5jZSBQb2ludHMKPiAoT1BQKSB0YWJsZToKPgo+ICBj bG9ja3MgPSA8JmNjdSBDTEtfQ1BVX0MwX0FDRT4sIDwmY2N1IENMS19DUFVfQzFfQUNFPiwgPCZj Y3UgQ0xLX0NQVV9DMF9UQ00+LAo+ICAgICAgICAgICAgICAgICAgICAgICAgIDwmY2N1IENMS19D Q0k1NTA+LCA8JmNjdSBDTEtfUExMMz4sIDwmY2N1Cj4gQ0xLX0NQVV9DMF9IST4sIDwmY2N1IENM S19DUFVfQzFfSEk+Owo+ICAgICAgICAgICAgICAgICBjbG9jay1uYW1lcyA9ICJhY2UwIiwiYWNl MSIsInRjbSIsImNjaSIsInBsbDMiLCAiYzBoaSIsICJjMWhpIjsKPgo+IFRoZXNlIGhhcmR3YXJl IGNsb2NrcyBhcmUgYWxzbyBleHBsaWNpdGx5IHJlZ2lzdGVyZWQgaW4gdGhlIEFQTVUgY2xvY2sg ZHJpdmVyCj4gdmlhIHRoZSBrMV9jY3VfYXBtdV9od3MgYXJyYXksIGNvbmZpcm1pbmcgdGhlaXIg YXZhaWxhYmlsaXR5IGZvciBmcmVxdWVuY3kKPiBhbmQgdm9sdGFnZSBzY2FsaW5nIG9uIHRoZSBL MS1YIFNvQy4KPgo+IHN0YXRpYyBzdHJ1Y3QgY2xrX2h3ICprMV9jY3VfYXBtdV9od3NbXSA9IHsK PiAgICAgICAgIFtDTEtfQ0NJNTUwXSAgICAgICAgICAgID0gJmNjaTU1MF9jbGsuY29tbW9uLmh3 LAo+ICAgICAgICAgW0NMS19DUFVfQzBfSEldICAgICAgICAgPSAmY3B1X2MwX2hpX2Nsay5jb21t b24uaHcsCj4gICAgICAgICBbQ0xLX0NQVV9DMF9DT1JFXSAgICAgICA9ICZjcHVfYzBfY29yZV9j bGsuY29tbW9uLmh3LAo+ICAgICAgICAgW0NMS19DUFVfQzBfQUNFXSAgICAgICAgPSAmY3B1X2Mw X2FjZV9jbGsuY29tbW9uLmh3LAo+ICAgICAgICAgW0NMS19DUFVfQzBfVENNXSAgICAgICAgPSAm Y3B1X2MwX3RjbV9jbGsuY29tbW9uLmh3LAo+ICAgICAgICAgW0NMS19DUFVfQzFfSEldICAgICAg ICAgPSAmY3B1X2MxX2hpX2Nsay5jb21tb24uaHcsCj4gICAgICAgICBbQ0xLX0NQVV9DMV9DT1JF XSAgICAgICA9ICZjcHVfYzFfY29yZV9jbGsuY29tbW9uLmh3LAo+ICAgICAgICAgW0NMS19DUFVf QzFfQUNFXSAgICAgICAgPSAmY3B1X2MxX2FjZV9jbGsuY29tbW9uLmh3LAo+Cj4gWWVzLCBpdCBp cyBwb3NzaWJsZSB0byBhZGQgdGhlc2UgY2xvY2tzIGZvciBEVkZTIHRvIHdvcmsgY29ycmVjdGx5 LAo+IHByb3ZpZGVkIHRoZXkgYXJlIG1hbmFnZWQgYnkgdGhlIGFwcHJvcHJpYXRlIGRyaXZlciBh bmQgZGVjbGFyZWQgaW4KPiB0aGUgRGV2aWNlIFRyZWUgKERUKS4KPgo+IFRoYW5rcwo+IC1BbmFu ZAoKVGhhbmtzIGZvciB5b3VyIHJldmlldyBhbmQgZm9yIHBvaW50aW5nIHRoaXMgb3V0LgoKUmVn YXJkaW5nIHRoZSBjbG9ja3MgeW91IG1lbnRpb25lZCwgSSdkIGxpa2UgdG8gY2xhcmlmeSB0aGVp ciByb2xlcyBiYXNlZCBvbgp0aGUgSzEgZGF0YXNoZWV0LiBUYWtpbmcgQ2x1c3RlciAwIGFzIGFu IGV4YW1wbGUsIGMwX2NvcmVfY2xrIGlzIHRoZSBwcmltYXJ5CmNsb2NrIGZvciB0aGUgY2x1c3Rl ci4gYzBfYWNlX2NsayBhbmQgYzBfdGNtX2NsayBhcmUgY2hpbGRyZW4gZGVyaXZlZCBmcm9tIGl0 LApkZWZhdWx0aW5nIHRvIGhhbGYgdGhlIGZyZXF1ZW5jeSBvZiB0aGVpciBwYXJlbnQgY29yZSBj bG9jaywgd2hpbGUgYzBfaGlfY2xrCnJlcHJlc2VudHMgdGhlIGhpZ2gtc3BlZWQgcGF0aCBzZWxl Y3Rpb24uCkNsdXN0ZXIgMSBmb2xsb3dzIHRoZSBzYW1lIHN0cnVjdHVyZS4KCkJhc2VkIG9uIHRo ZSBvZmZpY2lhbCBTcGFjZW1pVCBCaWFuYnUgT1Mgc291cmNlLCB0aGUgc3BhY2VtaXQtY3B1ZnJl cS5jIGRyaXZlcgptYWlubHkgcGVyZm9ybXMgdGhlIGZvbGxvd2luZyB0YXNrczoKMS4gU2V0cyB0 aGUgQ0NJNTUwIGNsb2NrIGZyZXF1ZW5jeSB0byA2MTRNSHouCjIuIFNldHMgdGhlIGNsb2NrIGZy ZXF1ZW5jaWVzIG9mIGMwX2FjZV9jbGssIGMxX2FjZTFfY2xrLCBhbmQgYzBfdGNtX2NsayB0byBo YWxmCnRoZSBmcmVxdWVuY3kgb2YgdGhlaXIgcGFyZW50IGNsb2NrLgozLiBGb3IgdGhlIDEuNkdI eiBPUFAsIGl0IHNldHMgdGhlIFBMTDMgZnJlcXVlbmN5IHRvIDMuMkdIeiBhbmQgdGhlCmMwX2hp X2Nsay9jMV9oaV9jbGsgZnJlcXVlbmNpZXMgdG8gMS42R0h6LgoKSSBib290ZWQgd2l0aCB0aGUg bWFudWZhY3R1cmVyJ3MgT3BlbldSVCBpbWFnZSBhbmQgdXNlZCBkZWJ1Z2ZzIHRvIGNvbmZpcm0g dGhhdAp0aGUgY2xvY2sgc3RhdGVzIGFyZSBleGFjdGx5IGFzIGRlc2NyaWJlZCBhYm92ZS4KCkF0 IDEuNkdIejoKQ2xvY2sgU291cmNlICYgVHJlZSAgICAgICAgICAgUmF0ZSAoSHopICAgICAgSFcg RW5hYmxlICBDb25zdW1lcgotLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KcGxsMyAgICAgICAgICAgICAgICAg ICAgICAgICAgMywyMDAsMDAwLDAwMCAgICAgIFkgICAgICBkZXZpY2VsZXNzCiDilJTilIAgcGxs M19kMiAgICAgICAgICAgICAgICAgICAxLDYwMCwwMDAsMDAwICAgICAgWSAgICAgIGRldmljZWxl c3MKICAgICDilJzilIAgY3B1X2MxX2hpX2NsayAgICAgICAgIDEsNjAwLDAwMCwwMDAgICAgICBZ ICAgICAgZGV2aWNlbGVzcwogICAgIOKUgiAgIOKUlOKUgCBjcHVfYzFfcGNsayAgICAgICAxLDYw MCwwMDAsMDAwICAgICAgWSAgICAgIGNwdTAKICAgICDilIIgICAgICAg4pSU4pSAIGNwdV9jMV9h Y2VfY2xrICA4MDAsMDAwLDAwMCAgICAgIFkgICAgICBkZXZpY2VsZXNzCiAgICAg4pSU4pSAIGNw dV9jMF9oaV9jbGsgICAgICAgICAxLDYwMCwwMDAsMDAwICAgICAgWSAgICAgIGRldmljZWxlc3MK ICAgICAgICAg4pSU4pSAIGNwdV9jMF9jb3JlX2NsayAgIDEsNjAwLDAwMCwwMDAgICAgICBZICAg ICAgY3B1MAogICAgICAgICAgICAg4pSc4pSAIGNwdV9jMF90Y21fY2xrICA4MDAsMDAwLDAwMCAg ICAgIFkgICAgICBkZXZpY2VsZXNzCiAgICAgICAgICAgICDilJTilIAgY3B1X2MwX2FjZV9jbGsg IDgwMCwwMDAsMDAwICAgICAgWSAgICAgIGRldmljZWxlc3MKCnBsbDFfMjQ1N3A2X3ZjbyAgICAg ICAgICAgICAgIDIsNDU3LDYwMCwwMDAgICAgICBZICAgICAgZGV2aWNlbGVzcwog4pSU4pSAIHBs bDFfZDQgICAgICAgICAgICAgICAgICAgICA2MTQsNDAwLDAwMCAgICAgIFkgICAgICBkZXZpY2Vs ZXNzCiAgICAg4pSU4pSAIHBsbDFfZDRfNjE0cDQgICAgICAgICAgIDYxNCw0MDAsMDAwICAgICAg WSAgICAgIGRldmljZWxlc3MKICAgICAgICAg4pSU4pSAIGNjaTU1MF9jbGsgICAgICAgICAgNjE0 LDQwMCwwMDAgICAgICBZICAgICAgZGV2aWNlbGVzcwoKQXQgMS4yMjhHSHo6CkNsb2NrIFNvdXJj ZSAmIFRyZWUgICAgICAgICAgIFJhdGUgKEh6KSAgICAgIEhXIEVuYWJsZSAgQ29uc3VtZXIKLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tCnBsbDFfMjQ1N3A2X3ZjbyAgICAgICAgICAgICAgIDIsNDU3LDYwMCww MDAgICAgICBZICAgICAgZGV2aWNlbGVzcwog4pSU4pSAIHBsbDFfZDIgICAgICAgICAgICAgICAg ICAgMSwyMjgsODAwLDAwMCAgICAgIFkgICAgICBkZXZpY2VsZXNzCiAgICAg4pSU4pSAIHBsbDFf ZDJfMTIyOHA4ICAgICAgICAxLDIyOCw4MDAsMDAwICAgICAgWSAgICAgIGRldmljZWxlc3MKICAg ICAgICAg4pSc4pSAIGNwdV9jMF9jb3JlX2NsayAgIDEsMjI4LDgwMCwwMDAgICAgICBZICAgICAg Y3B1MAogICAgICAgICDilIIgICDilJzilIAgY3B1X2MwX3RjbV9jbGsgIDYxNCw0MDAsMDAwICAg ICAgWSAgICAgIGRldmljZWxlc3MKICAgICAgICAg4pSCICAg4pSU4pSAIGNwdV9jMF9hY2VfY2xr ICA2MTQsNDAwLDAwMCAgICAgIFkgICAgICBkZXZpY2VsZXNzCiAgICAgICAgIOKUlOKUgCBjcHVf YzFfcGNsayAgICAgICAxLDIyOCw4MDAsMDAwICAgICAgWSAgICAgIGNwdTAKICAgICAgICAgICAg IOKUlOKUgCBjcHVfYzFfYWNlX2NsayAgNjE0LDQwMCwwMDAgICAgICBZICAgICAgZGV2aWNlbGVz cwogIOKUlOKUgCBwbGwxX2Q0ICAgICAgICAgICAgICAgICAgICAgNjE0LDQwMCwwMDAgICAgICBZ ICAgICAgZGV2aWNlbGVzcwogICAgIOKUlOKUgCBwbGwxX2Q0XzYxNHA0ICAgICAgICAgICA2MTQs NDAwLDAwMCAgICAgIFkgICAgICBkZXZpY2VsZXNzCiAgICAgICAgIOKUlOKUgCBjY2k1NTBfY2xr ICAgICAgICAgIDYxNCw0MDAsMDAwICAgICAgWSAgICAgIGRldmljZWxlc3MKCnBsbDMgICAgICAg ICAgICAgICAgICAgICAgICAgIDMsMjAwLDAwMCwwMDAgICAgICBZICAgICAgZGV2aWNlbGVzcwog 4pSU4pSAIHBsbDNfZDIgICAgICAgICAgICAgICAgICAgMSw2MDAsMDAwLDAwMCAgICAgIFkgICAg ICBkZXZpY2VsZXNzCiAgICAg4pSc4pSAIGNwdV9jMV9oaV9jbGsgICAgICAgICAxLDYwMCwwMDAs MDAwICAgICAgWSAgICAgIGRldmljZWxlc3MKICAgICDilJTilIAgY3B1X2MwX2hpX2NsayAgICAg ICAgIDEsNjAwLDAwMCwwMDAgICAgICBZICAgICAgZGV2aWNlbGVzcwog4pSU4pSAIHBsbDNfZDMg ICAgICAgICAgICAgICAgICAgMSwwNjYsNjY2LDY2NiAgICAgIFkgICAgICBkZXZpY2VsZXNzCgpS ZWdhcmRpbmcgdGhlIG5lY2Vzc2l0eSBvZiBsaXN0aW5nIHRoZXNlIGNsb2NrcyBpbiB0aGUgRFQs IG15IGFuYWx5c2lzIGlzIGFzIGZvbGxvd3M6CjEuIEZvciBDQ0k1NTAsIEkgZGlkIG5vdCBmaW5k IGEgY2xlYXIgZGVmaW5pdGlvbiBvZiB0aGlzIGNsb2NrJ3Mgc3BlY2lmaWMgcm9sZQppbiB0aGUg U29DIGRhdGFzaGVldC4gQWx0aG91Z2ggdGhlIHZlbmRvciBrZXJuZWwgaW5jcmVhc2VzIGl0cyBm cmVxdWVuY3ksCm15IGJlbmNobWFya3Mgc2hvdyB0aGF0IG1haW50YWluaW5nIHRoZSBtYWlubGlu ZSBkZWZhdWx0ICgyNDUuNzZNSHopIGhhcyBhCm5lZ2xpZ2libGUgaW1wYWN0IG9uIENQVSBwZXJm b3JtYW5jZS4KMi4gRm9yIEFDRSBhbmQgVENNIGNsb2NrcywgdGhleSBmdW5jdGlvbiBhcyBzeW5j aHJvbm91cyBjaGlsZHJlbiBvZiB0aGUgY29yZQpjbG9jayB3aXRoIGEgZGVmYXVsdCBkaXZpZGUt YnktMiByYXRpby4gU2luY2UgdGhleSBzY2FsZSBhdXRvbWF0aWNhbGx5IHJlbGF0aXZlCnRvIGMw X2NvcmVfY2xrL2MxX2NvcmVfY2xrIGFuZCBubyBvdGhlciBwZXJpcGhlcmFscyBkZXBlbmQgb24g dGhlbSwgdGhleSBkbyBub3QKcmVxdWlyZSBtYW51YWwgbWFuYWdlbWVudCBpbiB0aGUgT1BQIHRh YmxlLgozLiBGb3IgdGhlIGhpZ2gtc3BlZWQgcGF0aCwgdGhlIHVuZGVybHlpbmcgY2xvY2sgY29u dHJvbGxlciBsb2dpYyBhbHJlYWR5IGhhbmRsZXMKdGhlIHBhcmVudCBNVVggc3dpdGNoaW5nIGFu ZCBQTEwzIHNjYWxpbmcgYXV0b21hdGljYWxseSB3aGVuIGNsa19zZXRfcmF0ZSgpCmlzIGNhbGxl ZCBvbiB0aGUgY29yZSBjbG9jay4KCkkgaGF2ZSB2ZXJpZmllZCB0aGlzIGJ5IGNoZWNraW5nIHRo ZSBoYXJkd2FyZSBzdGF0ZSBpbiB0aGUgbWFpbmxpbmUga2VybmVsLgpUaGUgY2xvY2sgdHJlZSBt YXRjaGVzIHRoZSB2ZW5kb3Iga2VybmVsJ3MgY29uZmlndXJhdGlvbjoKCkF0IDEuNkdIejoKQ2xv Y2sgU291cmNlICYgVHJlZSAgICAgICAgICAgUmF0ZSAoSHopICAgICAgSFcgRW5hYmxlICBDb25z dW1lcgotLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KcGxsMyAgICAgICAgICAgICAgICAgICAgICAgICAgMywy MDAsMDAwLDAwMCAgICAgIFkgICAgICBkZXZpY2VsZXNzCiDilJTilIAgcGxsM19kMiAgICAgICAg ICAgICAgICAgICAxLDYwMCwwMDAsMDAwICAgICAgWSAgICAgIGRldmljZWxlc3MKICAgICDilJzi lIAgY3B1X2MxX2hpX2NsayAgICAgICAgIDEsNjAwLDAwMCwwMDAgICAgICBZICAgICAgZGV2aWNl bGVzcwogICAgIOKUgiAgIOKUlOKUgCBjcHVfYzFfY29yZV9jbGsgICAxLDYwMCwwMDAsMDAwICAg ICAgWSAgICAgIGNwdTQKICAgICDilIIgICAgICAg4pSU4pSAIGNwdV9jMV9hY2VfY2xrICA4MDAs MDAwLDAwMCAgICAgIFkgICAgICBkZXZpY2VsZXNzCiAgICAg4pSU4pSAIGNwdV9jMF9oaV9jbGsg ICAgICAgICAxLDYwMCwwMDAsMDAwICAgICAgWSAgICAgIGRldmljZWxlc3MKICAgICAgICAg4pSU 4pSAIGNwdV9jMF9jb3JlX2NsayAgIDEsNjAwLDAwMCwwMDAgICAgICBZICAgICAgY3B1MAogICAg ICAgICAgICAg4pSc4pSAIGNwdV9jMF90Y21fY2xrICA4MDAsMDAwLDAwMCAgICAgIFkgICAgICBk ZXZpY2VsZXNzCiAgICAgICAgICAgICDilJTilIAgY3B1X2MwX2FjZV9jbGsgIDgwMCwwMDAsMDAw ICAgICAgWSAgICAgIGRldmljZWxlc3MKCnBsbDEgICAgICAgICAgICAgICAgICAgICAgICAgIDIs NDU3LDYwMCwwMDAgICAgICBZICAgICAgZGV2aWNlbGVzcwog4pSU4pSAIHBsbDFfZDUgICAgICAg ICAgICAgICAgICAgICA0OTEsNTIwLDAwMCAgICAgIFkgICAgICBkZXZpY2VsZXNzCiAgICAg4pSU 4pSAIHBsbDFfZDVfNDkxcDUyICAgICAgICAgIDQ5MSw1MjAsMDAwICAgICAgWSAgICAgIGRldmlj ZWxlc3MKICAgICAgICAg4pSU4pSAIGNjaTU1MF9jbGsgICAgICAgICAgMjQ1LDc2MCwwMDAgICAg ICBZICAgICAgZGV2aWNlbGVzcwoKQXQgMS4yMjhHSHo6CkNsb2NrIFNvdXJjZSAmIFRyZWUgICAg ICAgICAgIFJhdGUgKEh6KSAgICAgIEhXIEVuYWJsZSAgQ29uc3VtZXIKLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tCnBsbDEgICAgICAgICAgICAgICAgICAgICAgICAgIDIsNDU3LDYwMCwwMDAgICAgICBZICAg ICAgZGV2aWNlbGVzcwog4pSc4pSAIHBsbDFfZDUgICAgICAgICAgICAgICAgICAgICA0OTEsNTIw LDAwMCAgICAgIFkgICAgICBkZXZpY2VsZXNzCiDilIIgICDilJTilIAgcGxsMV9kNV80OTFwNTIg ICAgICAgICAgNDkxLDUyMCwwMDAgICAgICBZICAgICAgZGV2aWNlbGVzcwog4pSCICAgICAgIOKU lOKUgCBjY2k1NTBfY2xrICAgICAgICAgIDI0NSw3NjAsMDAwICAgICAgWSAgICAgIGRldmljZWxl c3MKIOKUlOKUgCBwbGwxX2QyICAgICAgICAgICAgICAgICAgIDEsMjI4LDgwMCwwMDAgICAgICBZ ICAgICAgZGV2aWNlbGVzcwogICAgIOKUlOKUgCBwbGwxX2QyXzEyMjhwOCAgICAgICAgMSwyMjgs ODAwLDAwMCAgICAgIFkgICAgICBkZXZpY2VsZXNzCiAgICAgICAgIOKUlOKUgCBjcHVfYzBfY29y ZV9jbGsgICAxLDIyOCw4MDAsMDAwICAgICAgWSAgICAgIGNwdTAKICAgICAgICAgICAgIOKUnOKU gCBjcHVfYzBfdGNtX2NsayAgNjE0LDQwMCwwMDAgICAgICBZICAgICAgZGV2aWNlbGVzcwogICAg ICAgICAgICAg4pSU4pSAIGNwdV9jMF9hY2VfY2xrICA2MTQsNDAwLDAwMCAgICAgIFkgICAgICBk ZXZpY2VsZXNzCgpwbGwzICAgICAgICAgICAgICAgICAgICAgICAgICAzLDIwMCwwMDAsMDAwICAg ICAgWSAgICAgIGRldmljZWxlc3MKIOKUlOKUgCBwbGwzX2QyICAgICAgICAgICAgICAgICAgIDEs NjAwLDAwMCwwMDAgICAgICBZICAgICAgZGV2aWNlbGVzcwogICAgIOKUlOKUgCBjcHVfYzFfaGlf Y2xrICAgICAgICAgMSw2MDAsMDAwLDAwMCAgICAgIFkgICAgICBkZXZpY2VsZXNzCiAgICAgICAg IOKUlOKUgCBjcHVfYzFfY29yZV9jbGsgICAxLDYwMCwwMDAsMDAwICAgICAgWSAgICAgIGNwdTQK ICAgICAgICAgICAgIOKUlOKUgCBjcHVfYzFfYWNlX2NsayAgODAwLDAwMCwwMDAgICAgICBZICAg ICAgZGV2aWNlbGVzcwoKUGVyZm9ybWFuY2UgYmVuY2htYXJrcyBhbHNvIGNvbmZpcm0gdGhhdCB0 aGUgY3VycmVudCBjb25maWd1cmF0aW9uIGlzIHN1ZmZpY2llbnQ6CkJlbmNobWFyayAoQVdLIGNv bXB1dGF0aW9uKTogdGltZSBhd2sgJ0JFR0lOe2ZvcihpPTA7aTwxMDAwMDAwMDtpKyspIHN1bSs9 aX0nCi0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KRnJlcXVlbmN5ICAgIHwgICAgICBNYWlubGluZSBMaW51 eCAocykgICAgICAgfCAgICAgICAgT3BlbldydCAocykgICAgICAgICAgCihrSHopICAgICAgICB8 ICBSZWFsIChUb3RhbCkgfCAgVXNlciAoQ1BVKSAgIHwgIFJlYWwgKFRvdGFsKSB8ICBVc2VyIChD UFUpICkKLS0tLS0tLS0tLS0tLSstLS0tLS0tLS0tLS0tLS0rLS0tLS0tLS0tLS0tLS0tKy0tLS0t LS0tLS0tLS0tLSstLS0tLS0tLS0tLS0tLQoxLDYwMCwwMDAgICAgfCAgICAgMS44MnMgICAgIHwg ICAgIDEuODFzICAgICB8ICAgICAxLjczcyAgICAgfCAgICAxLjczcyAgICAKMSwyMjgsODAwICAg IHwgICAgIDIuMzRzICAgICB8ICAgICAyLjMzcyAgICAgfCAgICAgMi4yNnMgICAgIHwgICAgMi4y NnMgICAgCjEsMDAwLDAwMCAgICB8ICAgICAyLjk0cyAgICAgfCAgICAgMi44NnMgICAgIHwgICAg IDIuNzhzICAgICB8ICAgIDIuNzhzICAgIAogIDgxOSwwMDAgICAgfCAgICAgMy41NHMgICAgIHwg ICAgIDMuNTNzICAgICB8ICAgICAzLjM5cyAgICAgfCAgICAzLjM5cyAgICAKICA2MTQsNDAwICAg IHwgICAgIDQuNzNzICAgICB8ICAgICA0LjcxcyAgICAgfCAgICAgNC41MXMgICAgIHwgICAgNC41 MXMgICAgCi0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KCkluIHN1bW1hcnksIGJlY2F1c2UgdGhlIGNsb2Nr IGNvbnRyb2xsZXIgY29ycmVjdGx5IGhhbmRsZXMgdGhlIGludGVybmFsIGRpdmlkZXJzCmFuZCBw YXJlbnQgc3dpdGNoaW5nLCBkZWNsYXJpbmcgb25seSB0aGUgcHJpbWFyeSBjb3JlIGNsb2NrIGZv ciBlYWNoIENQVSBub2RlIGlzCnN1ZmZpY2llbnQgZm9yIGZ1bmN0aW9uYWwgRFZGUy4KCi0tIApC ZXN0IHJlZ2FyZHMsClNodXdlaSBXdQoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX18KbGludXgtcmlzY3YgbWFpbGluZyBsaXN0CmxpbnV4LXJpc2N2QGxpc3Rz LmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5m by9saW51eC1yaXNjdgo=