From: "Gary Guo" <gary@garyguo.net>
To: "Zhi Wang" <zhiw@nvidia.com>, "Alexandre Courbot" <acourbot@nvidia.com>
Cc: <rust-for-linux@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <dakr@kernel.org>,
<aliceryhl@google.com>, <bhelgaas@google.com>,
<kwilczynski@kernel.org>, <ojeda@kernel.org>, <boqun@kernel.org>,
<gary@garyguo.net>, <bjorn3_gh@protonmail.com>,
<lossin@kernel.org>, <a.hindborg@kernel.org>, <tmgross@umich.edu>,
<markus.probst@posteo.de>, <cjia@nvidia.com>, <smitra@nvidia.com>,
<ankita@nvidia.com>, <aniketa@nvidia.com>, <kwankhede@nvidia.com>,
<targupta@nvidia.com>, <joelagnelf@nvidia.com>,
<jhubbard@nvidia.com>, <kjaju@nvidia.com>, <zhiwang@kernel.org>
Subject: Re: [PATCH v3 1/1] rust: pci: add extended capability and SR-IOV support
Date: Mon, 20 Apr 2026 11:24:52 +0100 [thread overview]
Message-ID: <DHXWQQCC1T7P.31L43LB99DEOX@garyguo.net> (raw)
In-Reply-To: <20260420131356.189e7209@inno-dell>
On Mon Apr 20, 2026 at 11:13 AM BST, Zhi Wang wrote:
> On Mon, 13 Apr 2026 15:52:28 +0900
> "Alexandre Courbot" <acourbot@nvidia.com> wrote:
>
>> Hi Zhi,
>>
>> On Fri Apr 10, 2026 at 3:52 AM JST, Zhi Wang wrote:
>> <snip>
>> > +/// An extended PCI capability that implements [`Io`].
>> > +///
>> > +/// # Examples
>> > +///
>> > +/// ```no_run
>> > +/// use kernel::pci::{
>> > +/// self,
>> > +/// ExtSriovCapability, //
>> > +/// };
>> > +/// use kernel::io::Io;
>> > +///
>> > +/// fn probe_sriov(pdev: &pci::Device<kernel::device::Core>) ->
>> > Result<(), kernel::error::Error> { +/// let config =
>> > pdev.config_space_extended()?; +/// let sriov =
>> > ExtSriovCapability::find(&config)?; +///
>> > +/// let total_vfs = kernel::io_read!(&sriov, .total_vfs);
>> > +/// let vf_offset = kernel::io_read!(&sriov, .vf_offset);
>> > +/// let bar0 = kernel::io_read!(&sriov, .vf_bar[0]);
>> > +/// kernel::io_write!(&sriov, .num_vfs, 4u16);
>> > +/// let bar0_64 = sriov.read_vf_bar64(0)?;
>> > +///
>> > +/// Ok(())
>> > +/// }
>> > +/// ```
>> > +///
>> > +/// # Invariants
>> > +///
>> > +/// `ptr` is within the device's extended configuration space at a
>> > valid +/// capability. For sized `T`, the region is at least
>> > `size_of::<T>()` bytes. +pub struct ExtCapability<'a, T: ?Sized +
>> > KnownSize = Region<0>> {
>> > + config: &'a ConfigSpace<'a, Extended>,
>> > + ptr: *mut T,
>> > +}
>>
>> This strongly looks like this is reinventing `io::View`. :) Even the
>> internals look similar. Can you check whether `io::View` can replace
>> this type? This would remove all the macro business and impl blocks
>> and simplify this patch considerably.
>>
>
> Thanks for catching this. This should be updated with Gary's patches
> posted in the mailing list. Will address this in V4.
I'll rebase my series and resend this week.
Best,
Gary
next prev parent reply other threads:[~2026-04-20 10:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-09 18:52 [PATCH 0/1] Rust PCI capability infrastructure and SR-IOV support Zhi Wang
2026-04-09 18:52 ` [PATCH v3 1/1] rust: pci: add extended capability " Zhi Wang
2026-04-13 6:52 ` Alexandre Courbot
2026-04-20 10:13 ` Zhi Wang
2026-04-20 10:24 ` Gary Guo [this message]
2026-04-26 4:12 ` Alexandre Courbot
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