From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE5AA3B52F8 for ; Mon, 10 Aug 2026 10:16:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.51 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786356987; cv=none; b=o4CTBNYPNfGGgOL/6ejOapHzjZOzDgQfCow8MKp/DrHt1eIper7geObqvv2BfTVBhw2KPyi9UygJBpkOcTeEWePxSMcfUgGjd0x17kdgM0pwGhZ7poW+LKIZuAr8nI7DHp4w4mzJYef0It7AZGJmnpHfbLpQpjtJDkQ/htV5Ef4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786356987; c=relaxed/simple; bh=6/f9wmm2awoewJ0RJjhCNb25rGgSGL053o6mzKpTT4M=; h=Mime-Version:Content-Type:Date:Message-Id:To:Cc:Subject:From: References:In-Reply-To; b=NRScav7PWtdHhLwbL514micYg2QSfZl5eNp/jkW2YFaf5uZBL4ChQJSUFD8p41L0UDPOHyy/rUAyzm1EfadjPLTREKDIZpmpMmJymr1qZYAvQH+FyvMOmJxvZGXp79iHSTRRgZmGTVYWJv7sfOuwZ0pFT6jTnGFt1KeAxLxUOkI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=fK8c8oGp; arc=none smtp.client-ip=209.85.218.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="fK8c8oGp" Received: by mail-ej1-f51.google.com with SMTP id a640c23a62f3a-c1600d040e4so234241466b.1 for ; Mon, 10 Aug 2026 03:16:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1786356981; x=1786961781; darn=vger.kernel.org; h=in-reply-to:references:from:subject:cc:to:message-id:date :content-type:content-transfer-encoding:mime-version:from:to:cc :subject:date:message-id:reply-to:content-type; bh=0DdJ1gMHWzOjplPr4v+9JtrcaHIdGLk0WTVEXhfhPJg=; b=fK8c8oGpIFlqTtRA0txdBW/cTc3vYYR7auns6Dv2Ygd7T8VchqymaRk3esZaMM4dr0 fl6qDpx451wKA5s0FoPBbAGePzydjaGh5DpTIZErh1AH6iTTNKgJ/81khcZd5vrHUhQN F7AU3wSAuP694rIqtYQZLjIHL3Fs5ZkNldSMPyTRz5Ftbj8S8oATMk1AGSOkndz6z6xV fT46Uca4zOFrf+ZGXbs4D3agPRqOvn8IQK04zk4exqrR1GTRNkQKb6TChOsaE3PeAcIY OWWqP0TLVPm3zrsrhPU9AuEIFC8yurMUuJzMB7yQ7Su8kbnOKkUQBlwafCwIoR/peiwm NqEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786356981; x=1786961781; h=in-reply-to:references:from:subject:cc:to:message-id:date :content-type:content-transfer-encoding:mime-version:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=0DdJ1gMHWzOjplPr4v+9JtrcaHIdGLk0WTVEXhfhPJg=; b=m1upIveGO1/yUNwRDQJmUZTIF2nmTbIigBM2yl0C8QgP8rql7lodstEkexLvAVURZc gl3PoMHqzxjLQ/ax3vxsxQMdAv7hrJ+pVD+KMf5imLMAWtyQzXk7FJizzbctv+V/5cWo mE2ph8AsKeJqjT6SdabYM0ySAtUNd66k/CioHedRT36DOy7Hh8x0sJamIIU4nPT0qwYM STvXa5+17ZRzJanAwxbECzCTXIzYa0ROJUX1cCXv7xASX1chn6wmtIYu8qLeIk0zbda9 RMJD7cGtzq2+nTP/Zb7xv/xwOpHYtjBcFhDKMBYO4fPspigY0h7kw2isbbXpju5PyXYm 7UVg== X-Forwarded-Encrypted: i=1; AHgh+RryvVVFd0aRJdfiHU++UKMk3l5wCOPXB9r6QJOgNX6IwhXrM2E4NHEcmqBHuDY0ttW8WV9ABzwA+bWAeBY=@vger.kernel.org X-Gm-Message-State: AOJu0YyYfyjWaL7MAqUhkCpFbUtjFwb+s/j06orfeW0WAeVPtRnvjOwv 8cxbLQeGx9gzfUpRVWj4MApFF+V5u0Y91m+UJypXbE8f4vKs8huMe1+XFLxIl0ZuCVE= X-Gm-Gg: AR+sD11hC+VrybcdPQJ8SZMGzezWzPn2p1yQvrgj/N/jJKAvFB1wQF+zWR9D0SDkkJo vowWskcF5d0c/HzH39xp7DYwmuWSIUBp8kYTKzZx3gB6vQIKRRMNyXO00O3j2HpZXl0h4yOk9pT BnOCazRhOGCE3EmdZboFTXnIUGhCyO2eZCq3PedGDOEo4ATrkZhEin+7jcKRge3NAuGG3ifHgY6 fNjGXx7Lr3eZALLMGySHOT0g+bQKw1JSie45BpSaPKEFvgOvvaFsaDYHKhZcs/KLzLeWbpOouW4 AmIisFyH6P7b/r1HSfmshcqdoHiXhdzvGTmMFALqLISnA6sI/5552gb6Pp6cataSC7KX9GLZ57t OahLtLkTeU48+/jixzCCTtkaQQHAXz/TOn6NMkn1JslQfz3qcCoY5tvZCQqkUGUpG7BegXuIazm nXWBwIrXJrjyw+Efjaupy9px8JcRy0jC8FJwiXFYmOkeMnHosi+rrjg+ELThIP8666NiZPmVJ9V xXgTypHiGpDqdZd0nKW4cKpkFO64AIaYA== X-Received: by 2002:a17:907:94cc:b0:c1c:6d29:8a11 with SMTP id a640c23a62f3a-c208d3ec3cdmr919652366b.13.1786356981152; Mon, 10 Aug 2026 03:16:21 -0700 (PDT) Received: from localhost (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2080a29a33sm357250966b.2.2026.08.10.03.16.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Aug 2026 03:16:20 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 10 Aug 2026 12:16:19 +0200 Message-Id: To: "Dmitry Baryshkov" , "Joerg Roedel (AMD)" , "Will Deacon" , "Robin Murphy" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Konrad Dybcio" , "Rob Clark" , "Bjorn Andersson" , "Luca Weiss" Cc: , , , , Subject: Re: [PATCH 00/12] iommu: qcom_iommu: implement support for instances on MSM8974 From: "Luca Weiss" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260809-msm8974-iommu-upstream-v1-0-87f5cd492560@oss.qualcomm.com> In-Reply-To: <20260809-msm8974-iommu-upstream-v1-0-87f5cd492560@oss.qualcomm.com> Hi Dmitry, Many thanks for working on this and sending this patch series! On Sun Aug 9, 2026 at 10:15 PM CEST, Dmitry Baryshkov wrote: > Qualcomm MSM8974 platform has five SMMU instances, used by display, GPU, > Venus, VFE (camera) and JPEG encoder. Each of them follows ARM SMMU v1 > spec, however they differ from other Qualcomm platforms in the > implementation-specific registers and also in interaction with TZ. > Venus, MDP and VFE SMMUs are secured and require programming only of > CBs, while GPU and JPEG require full programming. > > This series skips IOMMUs which can't be tested right now (VFE and JPEG), > and adds only MDP, GPU and Venus (although untested, it is required for > display to work) SMMU instances. I do have a patch series (sent years ago to the mailing lists as well) for CAMSS so I can definitely test this in the future. > > Note, to get display to work properly one fix is necessary, [1] > > [1] https://patch.msgid.link/20260809-msm8974-mmcc-fix-v1-1-50f2dcf18d2e@= oss.qualcomm.com I've applied this series on v7.2-rc7, with the extra commits between that and linux-next for qcom_iommu.c backported so that your series applies without conflicts. So far I'm stuck with the GPU not being able to probe, adding some printk's shows that in msm_iommu_new() the call for iommu_attach_device() is failing. [ 5.971154] msm_mdp fd900100.display-controller: failed to load adreno g= pu [ 5.972991] msm_mdp fd900100.display-controller: failed to bind fdb00000= .gpu (ops a3xx_ops [msm]): -16 [ 5.974073] msm_mdp fd900100.display-controller: adev bind failed: -16 [ 5.974152] panel-s6d6fa1 fd922800.dsi.0: error -EBUSY: Failed to attach= to DSI host [ 5.974230] panel-s6d6fa1 fd922800.dsi.0: probe with driver panel-s6d6fa= 1 failed with error -16 ~ # dmesg | grep iommu [ 0.127014] iommu: Default domain type: Translated [ 0.127052] iommu: DMA domain TLB invalidation policy: strict mode [ 0.739899] platform fdb00000.gpu: Adding to iommu group 0 [ 0.741358] qcom-iommu fdc84000.iommu: iommu sec: pgtable size: 90112 [ 6.006877] platform fd900100.display-controller: Adding to iommu group = 1 Have you seen any issues like this? Regards Luca > > Signed-off-by: Dmitry Baryshkov > --- > Dmitry Baryshkov (12): > dt-bindings: iommu: qcom,iommu: document the MSM8974 IOMMUs > iommu: arm-smmu: add global register definitions used by the QSMMU > iommu: qcom_iommu: extract context bank programming into a helper > iommu: qcom_iommu: support the short-descriptor pagetable format > iommu: qcom_iommu: handle the SMMU global register space > iommu: qcom_iommu: support non-TZ-managed instances > iommu: qcom_iommu: restore context bank state after power collapse > iommu: qcom_iommu: halt the micro-MMU while programming context ban= ks > iommu: qcom_iommu: allow faulting transactions to terminate > iommu: qcom_iommu: program BFP (prefetch) settings > iommu: qcom_iommu: add the MSM8974 instances > ARM: dts: qcom: msm8974: add the IOMMUs > > .../devicetree/bindings/iommu/qcom,iommu.yaml | 16 +- > arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 85 +++- > drivers/iommu/arm/Kconfig | 1 + > drivers/iommu/arm/arm-smmu/arm-smmu.h | 10 + > drivers/iommu/arm/arm-smmu/qcom_iommu.c | 445 +++++++++++++++= ++++-- > 5 files changed, 517 insertions(+), 40 deletions(-) > --- > base-commit: 6c5c106bff878247a9cc7255077aab9040df8bf8 > change-id: 20260809-msm8974-iommu-upstream-144b1e2a15f0 > > Best regards, > -- =20 > With best wishes > Dmitry