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Expose > this information through the Rust PCI abstraction so drivers can use the > existing typed configuration-space accessors instead of raw bindings. > > Define ExtCapability to associate a capability ID with a register layout, > and add ConfigSpace::find_ext_capability() to locate and project that > layout. Bound the view at the next capability or the end of extended > configuration space. Add ExtSriovRegs and a decoded VF BAR iterator that > reads and validates all six VF BAR register slots up front, yields decode= d > BAR addresses and widths in logical order, and keeps the raw > configuration-space slot advancement internal. Since PCI_EXT_CAP_NEXT() i= s > a function-like macro, expose it through a Rust helper. > > Link: https://lore.kernel.org/rust-for-linux/20260730182954.783568-1-zhiw= @nvidia.com/ > Cc: Alexandre Courbot > Cc: Gary Guo > Signed-off-by: Zhi Wang > --- > rust/helpers/pci.c | 5 + > rust/kernel/pci.rs | 8 ++ > rust/kernel/pci/cap.rs | 317 +++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 330 insertions(+) > create mode 100644 rust/kernel/pci/cap.rs > > diff --git a/rust/helpers/pci.c b/rust/helpers/pci.c > index 4ebf256dff23..b946b14d79e4 100644 > --- a/rust/helpers/pci.c > +++ b/rust/helpers/pci.c > @@ -24,6 +24,11 @@ __rust_helper bool rust_helper_dev_is_pci(const struct= device *dev) > return dev_is_pci(dev); > } > =20 > +__rust_helper u32 rust_helper_pci_ext_cap_next(u32 header) > +{ > + return PCI_EXT_CAP_NEXT(header); > +} > + > #ifndef CONFIG_PCI_IOV > __rust_helper unsigned int > rust_helper_pci_sriov_get_totalvfs(struct pci_dev *pdev) > diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs > index 9f19ccd5905c..008c2770a3f3 100644 > --- a/rust/kernel/pci.rs > +++ b/rust/kernel/pci.rs > @@ -32,10 +32,18 @@ > }, > }; > =20 > +mod cap; > mod id; > mod io; > mod irq; > =20 > +pub use self::cap::{ > + ExtCapId, > + ExtCapability, > + ExtSriovCapability, > + ExtSriovRegs, > + ExtSriovVfBar, // > +}; > pub use self::id::{ > Class, > ClassMask, > diff --git a/rust/kernel/pci/cap.rs b/rust/kernel/pci/cap.rs > new file mode 100644 > index 000000000000..c49de8682f6d > --- /dev/null > +++ b/rust/kernel/pci/cap.rs > @@ -0,0 +1,317 @@ > +// SPDX-License-Identifier: GPL-2.0 > + > +//! PCI extended capability support. > + > +use super::{ > + io::ConfigSpaceBackend, > + ConfigSpace, > + Extended, // > +}; > +use crate::{ > + bindings, > + io::{ > + Io, > + IoBackend, > + Region, // > + }, > + num::Bounded, > + prelude::*, > +}; > + > +/// Number of VF BAR register slots in an SR-IOV capability. > +// CAST: `PCI_SRIOV_NUM_BARS` is 6, which fits in `usize`. > +const NUM_VF_BARS: usize =3D bindings::PCI_SRIOV_NUM_BARS as usize; > + > +/// PCI extended capability IDs. > +#[repr(u16)] > +#[derive(Debug, Clone, Copy, PartialEq, Eq)] > +pub enum ExtCapId { > + /// Single Root I/O Virtualization. > + // CAST: `PCI_EXT_CAP_ID_SRIOV` is `0x10`, which fits in `u16`. > + Sriov =3D bindings::PCI_EXT_CAP_ID_SRIOV as u16, > +} This might also make sense as a `struct` with assoc constants, so it can ac= cept unknown values. #[repr(transparent)] #[derive(...)] pub struct ExtCapId(u16); impl ExtCapId { pub const SRIOV: Self =3D Self(bindings::PCI_EXT_CAP_ID_SRIOV as u1= 6); } > + > +impl ExtCapId { > + #[inline] > + fn as_raw(self) -> u16 { > + self as u16 > + } > +} > + > +/// A typed PCI extended capability register layout. > +/// > +/// Implementors describe the register layout of one extended capability= . The layout must start at > +/// the extended capability header, and [`Self::ID`] must identify that = layout. > +pub trait ExtCapability: FromBytes + IntoBytes { > + /// PCI extended capability ID for this register layout. > + const ID: ExtCapId; > +} > + > +impl<'a> ConfigSpace<'a, Extended> { > + /// Finds and projects an extended capability into its typed registe= r layout. > + /// > + /// Returns [`None`] if the device does not implement the capability= . > + /// > + /// # Examples > + /// > + /// ```no_run > + /// use kernel::pci; > + /// > + /// fn probe_sriov( > + /// pdev: &pci::Device, > + /// ) -> Result<(), kernel::error::Error> { > + /// let Some(sriov) =3D pdev > + /// .config_space_extended()? > + /// .find_ext_capability::()? > + /// else { > + /// return Ok(()); > + /// }; > + /// > + /// let total_vfs =3D kernel::io_read!(sriov, .total_vfs); > + /// let vf_offset =3D kernel::io_read!(sriov, .vf_offset); > + /// let mut vf_bars =3D sriov.vf_bars()?; > + /// let bar0 =3D vf_bars.next().ok_or(kernel::error::code::EINVA= L)?; Error codes are in the prelude. > + /// let bar1 =3D vf_bars.next().ok_or(kernel::error::code::EINVA= L)?; > + /// let bar2 =3D vf_bars.next().ok_or(kernel::error::code::EINVA= L)?; > + /// > + /// Ok(()) > + /// } > + /// ``` > + pub fn find_ext_capability(&self) -> Result>> { > + let offset =3D usize::from( > + // SAFETY: `self.pdev` is valid by the type invariant of `Co= nfigSpace`. > + unsafe { > + bindings::pci_find_ext_capability(self.pdev.as_raw(), i3= 2::from(C::ID.as_raw())) > + }, > + ); > + > + if offset =3D=3D 0 { > + return Ok(None); > + } > + > + let size =3D self.calculate_ext_cap_size(offset)?; > + > + let base =3D ConfigSpaceBackend::as_ptr(*self) > + .cast::() > + .wrapping_add(offset); > + let ptr =3D Region::<0>::ptr_try_from_raw_parts_mut(base, size)?= ; > + > + // SAFETY: `offset` was returned by `pci_find_ext_capability`, a= nd > + // `calculate_ext_cap_size` bounds `ptr` at the next capability = or the end of the extended > + // configuration space. `ptr_try_from_raw_parts_mut` verified th= e region layout. > + let capability =3D unsafe { ConfigSpaceBackend::project_view(*se= lf, ptr) }; > + > + capability.try_cast::().map(Some) Is this cast failure is supposed to be error condition? > + } > + > + /// Calculates the size of the extended capability at `offset`. > + /// > + /// The capability extends to the next extended capability, or to th= e end of the extended > + /// configuration space if it is the last one. `offset` must be a DW= ORD-aligned offset within > + /// the extended configuration space returned by `pci_find_ext_capab= ility`. Returns an error if > + /// the capability header is outside the extended configuration spac= e. > + fn calculate_ext_cap_size(&self, offset: usize) -> Result { > + let header =3D self.try_read32(offset)?; > + // SAFETY: Pure bit manipulation, no preconditions. > + // CAST: The next-cap pointer is a 12-bit field (max 0xFFC), alw= ays fits in `usize`. > + let next =3D unsafe { bindings::pci_ext_cap_next(header) } as us= ize; > + > + Ok(if next > offset { > + next - offset > + } else { > + self.size() - offset > + }) > + } > +} > + > +/// SR-IOV register layout per PCIe spec (64 bytes starting at cap offse= t). > +#[repr(C)] > +#[derive(FromBytes, IntoBytes)] > +pub struct ExtSriovRegs { > + /// Extended capability header. > + pub header: u32, I think this shouldn't be public. > + /// SR-IOV capabilities. > + pub cap: u32, > + /// SR-IOV control. > + pub ctrl: u16, > + /// SR-IOV status. > + pub status: u16, > + /// Initial VFs. > + pub initial_vfs: u16, > + /// Total VFs. > + pub total_vfs: u16, > + /// Number of VFs. > + pub num_vfs: u16, > + /// Function dependency link. > + pub func_dep_link: u8, > + _reserved_0: u8, > + /// First VF offset. > + pub vf_offset: u16, > + /// VF stride. > + pub vf_stride: u16, > + _reserved_1: u16, > + /// VF device ID. > + pub vf_device_id: u16, > + /// Supported page sizes. > + pub supported_page_sizes: u32, > + /// System page size. > + pub system_page_size: u32, > + /// VF BARs (BAR0=E2=80=93BAR5). > + pub vf_bar: [u32; NUM_VF_BARS], > + /// VF migration state array offset. > + pub migration_state: u32, > +} > + > +impl ExtCapability for ExtSriovRegs { > + const ID: ExtCapId =3D ExtCapId::Sriov; > +} > + > +/// A typed view of an SR-IOV extended capability. > +pub type ExtSriovCapability<'a> =3D ConfigSpace<'a, ExtSriovRegs>; > + > +#[derive(Debug, Clone, Copy, PartialEq, Eq)] > +enum VfBarMemoryType { > + Bits32, > + Bits64, > +} > + > +impl TryFrom> for VfBarMemoryType { > + type Error =3D Error; > + > + fn try_from(value: Bounded) -> Result { > + match value.get() { > + 0b00 =3D> Ok(Self::Bits32), > + 0b10 =3D> Ok(Self::Bits64), > + _ =3D> Err(EINVAL), > + } > + } > +} > + > +impl From for Bounded { > + fn from(value: VfBarMemoryType) -> Self { > + match value { > + VfBarMemoryType::Bits32 =3D> Self::new::<0b00>(), > + VfBarMemoryType::Bits64 =3D> Self::new::<0b10>(), > + } > + } > +} > + > +crate::bitfield! { > + /// Low DWORD of an SR-IOV VF BAR. > + struct VfBarLow(u32) { > + /// Base address bits 31:4. > + 31:4 address; > + /// Whether the address range is prefetchable. > + 3:3 prefetchable =3D> bool; > + /// Memory BAR type. > + 2:1 memory_type ?=3D> VfBarMemoryType; > + /// Whether this is an I/O-space BAR. > + 0:0 io_space =3D> bool; > + } > +} > + > +/// A decoded VF BAR register encoding. > +#[derive(Debug, Clone, Copy, PartialEq, Eq)] > +pub struct ExtSriovVfBar { > + /// The BAR address without PCI attribute bits. > + pub address: u64, > + > + /// Whether the BAR is 64-bit. > + pub is_64bit: bool, > +} > + > +/// Iterator over decoded VF BAR register encodings. > +/// > +/// `slots` contains the six consecutive 32-bit registers VF BAR0 throug= h VF BAR5. A 32-bit > +/// memory BAR encoding uses one register. A 64-bit memory BAR encoding = uses that register for > +/// bits 31:0 and the immediately following register for bits 63:32. > +/// > +/// # Invariants > +/// > +/// - `config_slot <=3D NUM_VF_BARS`. > +/// - If `config_slot < NUM_VF_BARS`, it identifies the next register to= interpret as a BAR low > +/// DWORD. Its address-space encoding is memory and its type encoding = is either 32-bit or 64-bit. > +/// - If that low DWORD encodes a 64-bit BAR, `config_slot + 1 < NUM_VF_= BARS`, and the register at > +/// `config_slot + 1` is its upper DWORD. > +struct ExtSriovVfBars { > + slots: [u32; NUM_VF_BARS], > + config_slot: usize, > +} > + > +impl ExtSriovVfBars { > + fn new(slots: [u32; NUM_VF_BARS]) -> Result { > + let mut config_slot =3D 0; > + > + while config_slot < NUM_VF_BARS { > + let low =3D VfBarLow::from(slots[config_slot]); > + > + if low.io_space() { > + return Err(EINVAL); > + } > + > + let is_64bit =3D low.memory_type()? =3D=3D VfBarMemoryType::= Bits64; > + > + if is_64bit { > + if config_slot + 1 >=3D NUM_VF_BARS { > + return Err(EINVAL); > + } > + > + config_slot +=3D 2; > + } else { > + config_slot +=3D 1; > + } So you're already decoding the vf bars here, but the `next` does an additio= nal decoding. I think you should just decode them in one place. Best, Gary > + } > + > + Ok(Self { > + slots, > + config_slot: 0, > + }) > + } > +} > + > +impl Iterator for ExtSriovVfBars { > + type Item =3D ExtSriovVfBar; > + > + fn next(&mut self) -> Option { > + if self.config_slot >=3D NUM_VF_BARS { > + return None; > + } > + > + let config_slot =3D self.config_slot; > + let low =3D VfBarLow::from(self.slots[config_slot]); > + let is_64bit =3D matches!(low.memory_type(), Ok(VfBarMemoryType:= :Bits64)); > + let low_address =3D u64::from(low.address()) << VfBarLow::ADDRES= S_SHIFT; > + > + let address =3D if is_64bit { > + let high =3D self.slots[config_slot + 1]; > + self.config_slot +=3D 2; > + (u64::from(high) << 32) | low_address > + } else { > + self.config_slot +=3D 1; > + low_address > + }; > + > + Some(ExtSriovVfBar { address, is_64bit }) > + } > +} > + > +impl ExtSriovCapability<'_> { > + /// Returns an iterator over decoded VF BAR register encodings. > + /// > + /// The iterator tracks the six raw VF BAR register slots internally= . A 32-bit encoding yields > + /// one entry and advances by one slot; a 64-bit encoding combines t= wo slots into one entry. > + /// > + /// A zero-valued low DWORD is yielded as a 32-bit BAR at address ze= ro; this method does not > + /// probe whether a BAR is implemented. > + /// > + /// Returns [`EINVAL`] and logs an error if a BAR low DWORD does not= encode a 32-bit or 64-bit > + /// memory BAR, or if a 64-bit encoding has no upper DWORD. > + pub fn vf_bars(&self) -> Result> { > + let slots: [u32; NUM_VF_BARS] =3D > + core::array::from_fn(|slot| crate::io_read!(*self, .vf_bar[p= anic: slot])); > + > + ExtSriovVfBars::new(slots).inspect_err(|_| { > + dev_err!(self.pdev, "invalid VF BAR encoding in SR-IOV capab= ility\n"); > + }) > + } > +}