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[5.180.148.229]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499a9e784a4sm68071005e9.1.2026.08.19.08.10.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Aug 2026 08:10:46 -0700 (PDT) Precedence: bulk X-Mailing-List: oe-linux-nfc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 19 Aug 2026 17:10:45 +0200 Message-Id: Cc: , , , Subject: Re: [PATCH 3/3] arm64: dts: qcom: qcm6490-fairphone-fp5: add ST21NFCD NFC From: "Luca Weiss" To: "Kristian Brox" , X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260818205940.1973944-1-isyourbrainfoss@proton.me> <20260818205940.1973944-4-isyourbrainfoss@proton.me> In-Reply-To: <20260818205940.1973944-4-isyourbrainfoss@proton.me> Hi Kristian, Thanks for the patch! On Tue Aug 18, 2026 at 11:00 PM CEST, Kristian Brox wrote: > Enable the ST21NFCD on i2c9 (0x08), IRQ TLMM 41, reset TLMM 38 > active-high. Compatible is st,st21nfcd-i2c (raw NCI). ese-present and > uicc-present are unset; those links are unproven on this board. > > Signed-off-by: Kristian Brox > --- > diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/ar= m64/boot/dts/qcom/qcm6490-fairphone-fp5.dts > index d48cf38b7..a485edd24 100644 > --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts > +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts > @@ -1006,7 +1006,14 @@ redriver_ss_in: endpoint { > &i2c9 { > status =3D "okay"; > =20 > - /* ST21NFC NFC @ 28 */ > + nfc@8 { > + compatible =3D "st,st21nfcd-i2c"; > + reg =3D <0x08>; > + interrupt-parent =3D <&tlmm>; > + interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH>; > + reset-gpios =3D <&tlmm 38 GPIO_ACTIVE_HIGH>; GPIO 38 and 41 look correct. Some more things that probably should be described here: LN_BB_CLK2 from the SoC is connected to SYS_CLK from the chip, which is the reference clock input (clocks =3D <&rpmhcc RPMH_LN_BB_CLK2> ?). GPIO 39 is NFC_CLK_REQ, the External reference clock request signal Honestly not sure what it's for exactly. But if it's similar to [0], maybe it's irrelevant. For power supplies, L18B is VPS_IO (digital IO power supply) and L4C for VCC_UICC_IN (power supply for the UICC). I think at least VPS_IO should be modelled. VBAT and VDD_TX power inputs also exist, but they're both connected to VPH_PWR on FP5, not sure how much sense it makes to add them? And yes, as Konrad said, SWP_SE and SWP_UICC are connected to SIM1 and SIM2 respectively. [0] https://lore.kernel.org/all/20260811220135.472380-1-jorijnvdgraaf@catcr= afts.net/t/ Regards Luca > + }; > + > /* VL53L3 ToF @ 29 */ > }; > =20